diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-26 21:44:22 -0500 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-26 21:44:22 -0500 |
commit | c27c122afc6b778e67a9c77915fac71730a5a4ef (patch) | |
tree | 3056d2ebc1c9eb74fc8d850a942666ce46ad2026 /mem/physical.cc | |
parent | 4973a16b34471dcb5f65a1d6c31d5a7d8c2dfd83 (diff) | |
download | gem5-c27c122afc6b778e67a9c77915fac71730a5a4ef.tar.xz |
Add the bus and connector objects to scons
change getPort parameter from char* to string
Add an extra phase between construction and init called connect
SConscript:
Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
the connection to memory shouldn't be made until we know the memory
object exists (e.g. after construction)
dev/io_device.hh:
change to const string
mem/bus.hh:
change getPort parameter from char* to string
initialize num_interfaces
mem/mem_object.hh:
change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
change getPort parameter from char* to string
get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
Add an extra phase between construction and init called connect
--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
Diffstat (limited to 'mem/physical.cc')
-rw-r--r-- | mem/physical.cc | 27 |
1 files changed, 10 insertions, 17 deletions
diff --git a/mem/physical.cc b/mem/physical.cc index e6d1f1662..f16b79a8d 100644 --- a/mem/physical.cc +++ b/mem/physical.cc @@ -69,8 +69,8 @@ PhysicalMemory::MemResponseEvent::description() return "Physical Memory Timing Access respnse event"; } -PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus) - : MemObject(n), memPort(this), base_addr(0), pmem_addr(NULL) +PhysicalMemory::PhysicalMemory(const string &n) + : MemObject(n), base_addr(0), pmem_addr(NULL) { // Hardcoded to 128 MB for now. pmem_size = 1 << 27; @@ -88,14 +88,6 @@ PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus) } page_ptr = 0; - - Port *peer_port; - peer_port = bus->getPort(); - memPort.setPeer(peer_port); - peer_port->setPeer(&memPort); - - - } PhysicalMemory::~PhysicalMemory() @@ -160,10 +152,13 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt) } Port * -PhysicalMemory::getPort(const char *if_name) +PhysicalMemory::getPort(const std::string &if_name) { - if (if_name == NULL) { - return new MemoryPort(this); + if (if_name == "") { + if (port != NULL) + panic("PhysicalMemory::getPort: additional port requested to memory!"); + port = new MemoryPort(this); + return port; } else { panic("PhysicalMemory::getPort: unknown port %s requested", if_name); } @@ -341,7 +336,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) SimObjectParam<MemoryController *> mmu; #endif Param<Range<Addr> > range; - SimObjectParam<MemObject*> bus; END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory) @@ -351,8 +345,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) #if FULL_SYSTEM INIT_PARAM(mmu, "Memory Controller"), #endif - INIT_PARAM(range, "Device Address Range"), - INIT_PARAM(bus, "bus object memory connects to") + INIT_PARAM(range, "Device Address Range") END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory) @@ -364,7 +357,7 @@ CREATE_SIM_OBJECT(PhysicalMemory) } #endif - return new PhysicalMemory(getInstanceName(), bus); + return new PhysicalMemory(getInstanceName()); } REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory) |