Implement a very very simple bus

requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d

1 files changed, 23 insertions, 5 deletions

diff --git a/mem/physical.cc b/mem/physical.cc
index c1e83fb9e..e6d1f1662 100644
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -69,8 +69,8 @@ PhysicalMemory::MemResponseEvent::description()
     return "Physical Memory Timing Access respnse event";
 }
 
-PhysicalMemory::PhysicalMemory(const string &n)
-    : MemObject(n), base_addr(0), pmem_addr(NULL)
+PhysicalMemory::PhysicalMemory(const string &n, MemObject *bus)
+    : MemObject(n), memPort(this), base_addr(0), pmem_addr(NULL)
 {
     // Hardcoded to 128 MB for now.
     pmem_size = 1 << 27;
@@ -88,6 +88,14 @@ PhysicalMemory::PhysicalMemory(const string &n)
     }
 
     page_ptr = 0;
+
+    Port *peer_port;
+    peer_port = bus->getPort();
+    memPort.setPeer(peer_port);
+    peer_port->setPeer(&memPort);
+
+
+
 }
 
 PhysicalMemory::~PhysicalMemory()
@@ -181,7 +189,15 @@ void
 PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
                                            bool &owner)
 {
-    panic("??");
+    memory->getAddressRanges(range_list, owner);
+}
+
+void
+PhysicalMemory::getAddressRanges(AddrRangeList &range_list, bool &owner)
+{
+    owner = true;
+    range_list.clear();
+    range_list.push_back(RangeSize(base_addr, pmem_size));
 }
 
 int
@@ -325,6 +341,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
     SimObjectParam<MemoryController *> mmu;
 #endif
     Param<Range<Addr> > range;
+    SimObjectParam<MemObject*> bus;
 
 END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
 
@@ -334,7 +351,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
 #if FULL_SYSTEM
     INIT_PARAM(mmu, "Memory Controller"),
 #endif
-    INIT_PARAM(range, "Device Address Range")
+    INIT_PARAM(range, "Device Address Range"),
+    INIT_PARAM(bus, "bus object memory connects to")
 
 END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
 
@@ -346,7 +364,7 @@ CREATE_SIM_OBJECT(PhysicalMemory)
     }
 #endif
 
-    return new PhysicalMemory(getInstanceName());
+    return new PhysicalMemory(getInstanceName(), bus);
 }
 
 REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)