Add support for multiple ports on the memory. Hook up simple cpu to memory.

Ready to start testing if I could fix the linking errors I can't ever seem to fix.

cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Add connecting of ports until builder can handle it.
mem/physical.cc:
    Add function to allocate a port in the object

    Remove some full_sys stuff untill needed
mem/physical.hh:
    Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
    Update the params
sim/process.cc:
    Make sure to use the right name (hopefully CPU constructor already called)

--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85

1 files changed, 8 insertions, 3 deletions

diff --git a/mem/physical.hh b/mem/physical.hh
index b31e45ac5..fb2d0d743 100644
--- a/mem/physical.hh
+++ b/mem/physical.hh
@@ -37,7 +37,8 @@
 #include "mem/packet.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
-
+#include <map>
+#include <string>
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
 //
@@ -67,10 +68,14 @@ class PhysicalMemory : public Memory
         virtual int deviceBlockSize();
     };
 
-    MemoryPort memoryPort;
+    std::map<std::string, MemoryPort*> memoryPortList;
 
     Port * PhysicalMemory::getPort(const char *if_name);
 
+    Port * addPort(std::string portName);
+
+    int numPorts;
+
     int lat;
 
     struct MemResponseEvent : public Event
@@ -114,7 +119,7 @@ class PhysicalMemory : public Memory
     // fast back-door memory access for vtophys(), remote gdb, etc.
     // uint64_t phys_read_qword(Addr addr) const;
   private:
-    bool doTimingAccess(Packet &pkt);
+    bool doTimingAccess(Packet &pkt, MemoryPort *memoryPort);
     Tick doAtomicAccess(Packet &pkt);
     void doFunctionalAccess(Packet &pkt);