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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-18 22:54:19 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-18 22:54:19 -0400 |
| commit | 86777c9db174c74be49667bce3dda99f8ba23696 (patch) | |
| tree | 977260677d5e3f726811d919a0b1a36251398a59 /mem/request.hh | |
| parent | 796fa429fef8b038278c4a020374149d8b5ef8eb (diff) | |
| download | gem5-86777c9db174c74be49667bce3dda99f8ba23696.tar.xz | |
First steps toward getting full system to work with
TimingSimpleCPU. Not there yet.
cpu/simple/atomic.cc:
Only read SC result if store was an SC.
Don't fake SC here; fake it in PhysicalMemory so
all CPU models can share in the joy.
cpu/simple/timing.cc:
Don't forget to checkForInterrupts().
Only fetch subsequent instruction if we're still running
(i.e. not quiesced).
dev/io_device.hh:
Initialize port pointer in SendEvent object.
mem/physical.cc:
Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
Initialize flags to all clear, not uninitialized.
Otherwise we can't reliably look at flags w/o explicitly
setting them every time we create a request.
--HG--
extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6
Diffstat (limited to 'mem/request.hh')
| -rw-r--r-- | mem/request.hh | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/mem/request.hh b/mem/request.hh index 903e7503c..2db7b7779 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -97,8 +97,6 @@ class Request /** Flag structure for the request. */ uint32_t flags; - /** Wether or not flags is valid (has been written yet). */ - bool validFlags; //Accsesors for non-cpu request fields public: |