Implement a very very simple bus

requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d

1 files changed, 1 insertions, 5 deletions

diff --git a/mem/request.hh b/mem/request.hh
index 1c65057a0..5e2275741 100644
--- a/mem/request.hh
+++ b/mem/request.hh
@@ -73,11 +73,7 @@ class Request
     int size;
 
     /** The time this request was started. Used to calculate latencies. */
-    Tick requestTime;
-
-    /** The time this request was responded to in the memory hierachy. Used by
-     * deviced to inform ports how long a request should be delayed. */
-    Tick responseTime;
+    Tick time;
 
     /** Destination address if this is a block copy. */
     Addr copyDest;