More progress toward compiling... partly by

fixing things, partly by ignoring CPU models
that don't currently compile.

SConscript:
    Split sources for fast, simple, and o3 CPU models into
    separate source lists.  For now none of these are included
    in the base source list, so you won't get any CPU models
    at all... but we still can't compile the other stuff so
    it's not an issue.

    Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
    FunctionalMemory -> Memory
cpu/pc_event.hh:
    Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move Port functions into .cc file.
mem/port.hh:
    Make recvAddressRangesQuery panic by default instead
    of being abstract... do CPUs need to implement this?
mem/request.hh:
    Add prefetch flags.
sim/syscall_emul.hh:
    Start to fix...

--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7

1 files changed, 4 insertions, 0 deletions

diff --git a/mem/request.hh b/mem/request.hh
index 24296f1df..c3c1d0fd4 100644
--- a/mem/request.hh
+++ b/mem/request.hh
@@ -54,6 +54,10 @@ const unsigned ALTMODE		= 0x008;
 const unsigned UNCACHEABLE	= 0x010;
 /** The request should not cause a page fault. */
 const unsigned NO_FAULT         = 0x020;
+/** The request should be prefetched into the exclusive state. */
+const unsigned PF_EXCLUSIVE	= 0x100;
+/** The request should be marked as LRU. */
+const unsigned EVICT_NEXT	= 0x200;
 
 class Request
 {