summaryrefslogtreecommitdiff
path: root/mem/translating_port.hh
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2006-03-30 15:59:49 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-30 15:59:49 -0500
commite196d20d9d047a869e1d853fd02077b1d909a576 (patch)
tree3b45bd223ff1d144af5f94fc9431f01b8a0bad61 /mem/translating_port.hh
parent0b2deb2a8897fa857d2b3e1936401c6666fdc728 (diff)
downloadgem5-e196d20d9d047a869e1d853fd02077b1d909a576.tar.xz
Make TranslatingPort be a type of Port rather than something special
arch/alpha/arguments.cc: rather than returning 0, put a panic in... it will actually make us fix this rather than scratching our respective heads base/loader/object_file.cc: base/loader/object_file.hh: Object loader now takes a port rather than a translating port cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: sim/process.cc: Make translating port a type of port rather than anything special cpu/simple/cpu.cc: no need to grab a port from the cpu anymore mem/physical.cc: add an additional type of port to physicalmemory called "functional" Only used for functional accesses (loading binaries/syscall emu) mem/port.hh: make readBlok/writeBlob virtual so translating port can do the translation first mem/translating_port.cc: mem/translating_port.hh: Make TranslatingPort inherit from Port sim/system.cc: header file that doesn't exit removed --HG-- extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
Diffstat (limited to 'mem/translating_port.hh')
-rw-r--r--mem/translating_port.hh25
1 files changed, 16 insertions, 9 deletions
diff --git a/mem/translating_port.hh b/mem/translating_port.hh
index 2ba3d68e2..f6ad3ebb9 100644
--- a/mem/translating_port.hh
+++ b/mem/translating_port.hh
@@ -29,34 +29,41 @@
#ifndef __MEM_TRANSLATING_PROT_HH__
#define __MEM_TRANSLATING_PROT_HH__
-class Port;
+#include "mem/port.hh"
+
class PageTable;
-class TranslatingPort
+class TranslatingPort : public Port
{
private:
- Port *port;
PageTable *pTable;
+ bool allocating;
TranslatingPort(const TranslatingPort &specmem);
const TranslatingPort &operator=(const TranslatingPort &specmem);
public:
- TranslatingPort(Port *_port, PageTable *p_table);
+ TranslatingPort(PageTable *p_table, bool alloc = false);
virtual ~TranslatingPort();
public:
bool tryReadBlob(Addr addr, uint8_t *p, int size);
- bool tryWriteBlob(Addr addr, uint8_t *p, int size, bool alloc = false);
- bool tryMemsetBlob(Addr addr, uint8_t val, int size, bool alloc = false);
+ bool tryWriteBlob(Addr addr, uint8_t *p, int size);
+ bool tryMemsetBlob(Addr addr, uint8_t val, int size);
bool tryWriteString(Addr addr, const char *str);
bool tryReadString(std::string &str, Addr addr);
- void readBlob(Addr addr, uint8_t *p, int size);
- void writeBlob(Addr addr, uint8_t *p, int size, bool alloc = false);
- void memsetBlob(Addr addr, uint8_t val, int size, bool alloc = false);
+ virtual void readBlob(Addr addr, uint8_t *p, int size);
+ virtual void writeBlob(Addr addr, uint8_t *p, int size);
+ virtual void memsetBlob(Addr addr, uint8_t val, int size);
void writeString(Addr addr, const char *str);
void readString(std::string &str, Addr addr);
+
+ virtual bool recvTiming(Packet &pkt) { panic("TransPort is UniDir"); }
+ virtual Tick recvAtomic(Packet &pkt) { panic("TransPort is UniDir"); }
+ virtual void recvFunctional(Packet &pkt) { panic("TransPort is UniDir"); }
+ virtual void recvStatusChange(Status status) {panic("TransPort is UniDir");}
+
};
#endif