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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-16 17:36:50 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-05-16 17:36:50 -0400 |
commit | 309e1d81939c44f6b31795be84868605e05b09ec (patch) | |
tree | 1f079bbcb38e79b3221e59cf03c43dd2bd174770 /mem | |
parent | 2db12b3d6cdcb840ef41dbe3e4a8db1821d7c4de (diff) | |
download | gem5-309e1d81939c44f6b31795be84868605e05b09ec.tar.xz |
Split SimpleCPU into two different models, AtomicSimpleCPU and
TimingSimpleCPU, which use atomic and timing memory accesses
respectively. Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.
arch/alpha/isa/main.isa:
Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
Change completeAcc() methods to take Packet object pointers.
Also split out StoreCond template for completeAcc(), since
that's the only one that needs write_result and we get an
unused variable warning if we always have it in there.
build/SConstruct:
Update list of recognized CPU model names.
configs/test/test.py:
Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
Define sources for new CPU models.
Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
Bus needs to be able to route timing packets based on explicit dest
so responses can get back to requester. Set dest to Packet::Broadcast
to indicate that dest should be derived from address.
Also set packet src field based on port from which packet is sent.
mem/bus.hh:
Set packet src field based on port from which packet is sent.
mem/packet.hh:
Define Broadcast destination address to indicate that
packet should be routed based on address.
mem/physical.cc:
Set packet dest on response so packet is routed
back to requester properly.
mem/port.cc:
Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
Change default latency to be 1 cycle.
--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
Diffstat (limited to 'mem')
-rw-r--r-- | mem/bus.cc | 21 | ||||
-rw-r--r-- | mem/bus.hh | 18 | ||||
-rw-r--r-- | mem/packet.hh | 2 | ||||
-rw-r--r-- | mem/physical.cc | 1 | ||||
-rw-r--r-- | mem/port.cc | 2 |
5 files changed, 29 insertions, 15 deletions
diff --git a/mem/bus.cc b/mem/bus.cc index acc941434..f84e38301 100644 --- a/mem/bus.cc +++ b/mem/bus.cc @@ -48,9 +48,16 @@ Bus::init() /** Function called by the port when the bus is recieving a Timing * transaction.*/ bool -Bus::recvTiming(Packet &pkt, int id) +Bus::recvTiming(Packet &pkt) { - return findPort(pkt.addr, id)->sendTiming(pkt); + Port *port; + if (pkt.dest == Packet::Broadcast) { + port = findPort(pkt.addr, pkt.src); + } else { + assert(pkt.dest > 0 && pkt.dest < interfaces.size()); + port = interfaces[pkt.dest]; + } + return port->sendTiming(pkt); } Port * @@ -82,17 +89,19 @@ Bus::findPort(Addr addr, int id) /** Function called by the port when the bus is recieving a Atomic * transaction.*/ Tick -Bus::recvAtomic(Packet &pkt, int id) +Bus::recvAtomic(Packet &pkt) { - return findPort(pkt.addr, id)->sendAtomic(pkt); + assert(pkt.dest == Packet::Broadcast); + return findPort(pkt.addr, pkt.src)->sendAtomic(pkt); } /** Function called by the port when the bus is recieving a Functional * transaction.*/ void -Bus::recvFunctional(Packet &pkt, int id) +Bus::recvFunctional(Packet &pkt) { - findPort(pkt.addr, id)->sendFunctional(pkt); + assert(pkt.dest == Packet::Broadcast); + findPort(pkt.addr, pkt.src)->sendFunctional(pkt); } /** Function called by the port when the bus is recieving a status change.*/ diff --git a/mem/bus.hh b/mem/bus.hh index de9259a90..40d274037 100644 --- a/mem/bus.hh +++ b/mem/bus.hh @@ -57,15 +57,15 @@ class Bus : public MemObject /** Function called by the port when the bus is recieving a Timing transaction.*/ - bool recvTiming(Packet &pkt, int id); + bool recvTiming(Packet &pkt); /** Function called by the port when the bus is recieving a Atomic transaction.*/ - Tick recvAtomic(Packet &pkt, int id); + Tick recvAtomic(Packet &pkt); /** Function called by the port when the bus is recieving a Functional transaction.*/ - void recvFunctional(Packet &pkt, int id); + void recvFunctional(Packet &pkt); /** Function called by the port when the bus is recieving a status change.*/ void recvStatusChange(Port::Status status, int id); @@ -77,8 +77,7 @@ class Bus : public MemObject * loops) * @return pointer to port that the packet should be sent out of. */ - Port * - Bus::findPort(Addr addr, int id); + Port *findPort(Addr addr, int id); /** Process address range request. * @param resp addresses that we can respond to @@ -110,17 +109,17 @@ class Bus : public MemObject /** When reciving a timing request from the peer port (at id), pass it to the bus. */ virtual bool recvTiming(Packet &pkt) - { return bus->recvTiming(pkt, id); } + { pkt.src = id; return bus->recvTiming(pkt); } /** When reciving a Atomic requestfrom the peer port (at id), pass it to the bus. */ virtual Tick recvAtomic(Packet &pkt) - { return bus->recvAtomic(pkt, id); } + { pkt.src = id; return bus->recvAtomic(pkt); } /** When reciving a Functional requestfrom the peer port (at id), pass it to the bus. */ virtual void recvFunctional(Packet &pkt) - { bus->recvFunctional(pkt, id); } + { pkt.src = id; bus->recvFunctional(pkt); } /** When reciving a status changefrom the peer port (at id), pass it to the bus. */ @@ -131,7 +130,8 @@ class Bus : public MemObject // downstream from this bus, yes? That is, the union of all // the 'owned' address ranges of all the other interfaces on // this bus... - virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) + virtual void getDeviceAddressRanges(AddrRangeList &resp, + AddrRangeList &snoop) { bus->addressRanges(resp, snoop, id); } // Hack to make translating port work without changes diff --git a/mem/packet.hh b/mem/packet.hh index 69d00675d..ab961e304 100644 --- a/mem/packet.hh +++ b/mem/packet.hh @@ -121,6 +121,8 @@ struct Packet /** A index of the source of the transaction. */ short src; + static const short Broadcast = -1; + /** A index to the destination of the transaction. */ short dest; diff --git a/mem/physical.cc b/mem/physical.cc index beb97307a..d0409995b 100644 --- a/mem/physical.cc +++ b/mem/physical.cc @@ -127,6 +127,7 @@ PhysicalMemory::doTimingAccess (Packet &pkt, MemoryPort* memoryPort) { doFunctionalAccess(pkt); + pkt.dest = pkt.src; MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort); response->schedule(curTick + lat); diff --git a/mem/port.cc b/mem/port.cc index 32031d96c..5b1f634d6 100644 --- a/mem/port.cc +++ b/mem/port.cc @@ -31,6 +31,7 @@ */ #include "base/chunk_generator.hh" +#include "mem/packet_impl.hh" #include "mem/port.hh" void @@ -40,6 +41,7 @@ Port::blobHelper(Addr addr, uint8_t *p, int size, Command cmd) Packet pkt; pkt.req = &req; pkt.cmd = cmd; + pkt.dest = Packet::Broadcast; for (ChunkGenerator gen(addr, size, peerBlockSize()); !gen.done(); gen.next()) { |