Add a functional port that is used to load the original binaries in FS

SE mode now has a port that goes to whatever toplevel mem object the
CPU sees that does the appropriate translation for syscall emulation

SConscript:
    translating port is a syscall emu only source
arch/alpha/system.cc:
base/loader/object_file.cc:
base/loader/object_file.hh:
    Use the new functional port to write the binaries into memory
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
    We aren't always going to be writing straight to memory with syscalls
    support writing to a cache
mem/port.hh:
    Add a simple unidirectional functional port that panics on any incoming requests
mem/translating_port.hh:
    make translating port inherit from the simple port
sim/system.cc:
sim/system.hh:
    Add a functional port that is used to load the original binaries

--HG--
extra : convert_revision : 9096866d0b23e3aceea68394abb76e63c0f8fd8d

2 files changed, 18 insertions, 8 deletions

diff --git a/mem/port.hh b/mem/port.hh
index 67e259557..1884e96bf 100644
--- a/mem/port.hh
+++ b/mem/port.hh
@@ -165,8 +165,8 @@ class Port
 
     /** Function called by the associated device to send a functional access,
         an access in which the data is instantly updated everywhere in the
-        memory system, without affecting the current state of any block
-        or moving the block.
+        memory system, without affecting the current state of any block or
+        moving the block.
     */
     void sendFunctional(Packet &pkt)
         { return peer->recvFunctional(pkt); }
@@ -220,4 +220,19 @@ class Port
     void blobHelper(Addr addr, uint8_t *p, int size, Command cmd);
 };
 
+/** A simple functional port that is only meant for one way communication to
+ * physical memory. It is only meant to be used to load data into memory before
+ * the simulation begins.
+ */
+
+class FunctionalPort : public Port
+{
+  public:
+    virtual bool recvTiming(Packet &pkt) { panic("FuncPort is UniDir"); }
+    virtual Tick recvAtomic(Packet &pkt) { panic("FuncPort is UniDir"); }
+    virtual void recvFunctional(Packet &pkt) { panic("FuncPort is UniDir"); }
+    virtual void recvStatusChange(Status status) {panic("FuncPort is UniDir");}
+};
+
+
 #endif //__MEM_PORT_HH__
diff --git a/mem/translating_port.hh b/mem/translating_port.hh
index f6ad3ebb9..7611ac3c7 100644
--- a/mem/translating_port.hh
+++ b/mem/translating_port.hh
@@ -33,7 +33,7 @@
 
 class PageTable;
 
-class TranslatingPort : public Port
+class TranslatingPort : public FunctionalPort
 {
   private:
     PageTable *pTable;
@@ -59,11 +59,6 @@ class TranslatingPort : public Port
     void writeString(Addr addr, const char *str);
     void readString(std::string &str, Addr addr);
 
-    virtual bool recvTiming(Packet &pkt) { panic("TransPort is UniDir"); }
-    virtual Tick recvAtomic(Packet &pkt) { panic("TransPort is UniDir"); }
-    virtual void recvFunctional(Packet &pkt) { panic("TransPort is UniDir"); }
-    virtual void recvStatusChange(Status status) {panic("TransPort is UniDir");}
-
 };
 
 #endif