First steps toward getting full system to work with

TimingSimpleCPU.  Not there yet.

cpu/simple/atomic.cc:
    Only read SC result if store was an SC.
    Don't fake SC here; fake it in PhysicalMemory so
    all CPU models can share in the joy.
cpu/simple/timing.cc:
    Don't forget to checkForInterrupts().
    Only fetch subsequent instruction if we're still running
    (i.e. not quiesced).
dev/io_device.hh:
    Initialize port pointer in SendEvent object.
mem/physical.cc:
    Move fake SC "implementation" here from AtomicSimpleCPU.
mem/request.hh:
    Initialize flags to all clear, not uninitialized.
    Otherwise we can't reliably look at flags w/o explicitly
    setting them every time we create a request.

--HG--
extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6

2 files changed, 5 insertions, 2 deletions

diff --git a/mem/physical.cc b/mem/physical.cc
index 8de9c3203..bc2500678 100644
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -155,6 +155,11 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
       case Write:
         memcpy(pmem_addr + pkt->addr - base_addr, pkt->getPtr<uint8_t>(),
                 pkt->size);
+        // temporary hack: will need to add real LL/SC implementation
+        // for cacheless systems later.
+        if (pkt->req->getFlags() & LOCKED) {
+            pkt->req->setScResult(1);
+        }
         break;
       default:
         panic("unimplemented");
diff --git a/mem/request.hh b/mem/request.hh
index 903e7503c..2db7b7779 100644
--- a/mem/request.hh
+++ b/mem/request.hh
@@ -97,8 +97,6 @@ class Request
 
     /** Flag structure for the request. */
     uint32_t flags;
-    /** Wether or not flags is valid (has been written yet). */
-    bool validFlags;
 
 //Accsesors for non-cpu request fields
   public: