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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-15 17:52:49 -0500 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-15 17:52:49 -0500 |
commit | b8a2d1e5c78eac41125a0be0bc2b5d5fe4714684 (patch) | |
tree | 5d9fbf42459bc67d17cbfeaf36cda53a0068d308 /mem | |
parent | 091e6b72cf9f6c81b44d1d871c34907ad2615e6c (diff) | |
download | gem5-b8a2d1e5c78eac41125a0be0bc2b5d5fe4714684.tar.xz |
More progress toward compiling... partly by
fixing things, partly by ignoring CPU models
that don't currently compile.
SConscript:
Split sources for fast, simple, and o3 CPU models into
separate source lists. For now none of these are included
in the base source list, so you won't get any CPU models
at all... but we still can't compile the other stuff so
it's not an issue.
Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
FunctionalMemory -> Memory
cpu/pc_event.hh:
Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move Port functions into .cc file.
mem/port.hh:
Make recvAddressRangesQuery panic by default instead
of being abstract... do CPUs need to implement this?
mem/request.hh:
Add prefetch flags.
sim/syscall_emul.hh:
Start to fix...
--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
Diffstat (limited to 'mem')
-rw-r--r-- | mem/port.hh | 2 | ||||
-rw-r--r-- | mem/request.hh | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/mem/port.hh b/mem/port.hh index 6b32adb57..4e335e17c 100644 --- a/mem/port.hh +++ b/mem/port.hh @@ -121,7 +121,7 @@ class Port need to use two different ports. */ virtual void recvAddressRangesQuery(std::list<Range<Addr> > &range_list, - bool &owner) = 0; + bool &owner) { panic("??"); } public: diff --git a/mem/request.hh b/mem/request.hh index 24296f1df..c3c1d0fd4 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -54,6 +54,10 @@ const unsigned ALTMODE = 0x008; const unsigned UNCACHEABLE = 0x010; /** The request should not cause a page fault. */ const unsigned NO_FAULT = 0x020; +/** The request should be prefetched into the exclusive state. */ +const unsigned PF_EXCLUSIVE = 0x100; +/** The request should be marked as LRU. */ +const unsigned EVICT_NEXT = 0x200; class Request { |