Replace Memory with MemObject; no need for two different levels of hierarchy there.

Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f

4 files changed, 46 insertions, 20 deletions

diff --git a/mem/mem_object.cc b/mem/mem_object.cc
new file mode 100644
index 000000000..f579a0727
--- /dev/null
+++ b/mem/mem_object.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/mem_object.hh"
+#include "sim/param.hh"
+
+MemObject::MemObject(const std::string &name)
+    : SimObject(name)
+{
+}
+
+DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
diff --git a/mem/physical.cc b/mem/physical.cc
index a00c59139..c1e83fb9e 100644
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -70,7 +70,7 @@ PhysicalMemory::MemResponseEvent::description()
 }
 
 PhysicalMemory::PhysicalMemory(const string &n)
-    : Memory(n), base_addr(0), pmem_addr(NULL)
+    : MemObject(n), base_addr(0), pmem_addr(NULL)
 {
     // Hardcoded to 128 MB for now.
     pmem_size = 1 << 27;
@@ -107,13 +107,6 @@ PhysicalMemory::new_page()
     return return_addr;
 }
 
-Port *
-PhysicalMemory::addPort(std::string portName)
-{
-    memoryPortList[portName] = new MemoryPort(this);
-    return memoryPortList[portName];
-}
-
 int
 PhysicalMemory::deviceBlockSize()
 {
@@ -161,10 +154,11 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
 Port *
 PhysicalMemory::getPort(const char *if_name)
 {
-    if (memoryPortList.find(if_name) != memoryPortList.end())
-        return memoryPortList[if_name];
-    else
-        panic("Looking for a port that didn't exist\n");
+    if (if_name == NULL) {
+        return new MemoryPort(this);
+    } else {
+        panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
+    }
 }
 
 void
diff --git a/mem/physical.hh b/mem/physical.hh
index 658ba18ff..b066d3dfc 100644
--- a/mem/physical.hh
+++ b/mem/physical.hh
@@ -33,16 +33,17 @@
 #define __PHYSICAL_MEMORY_HH__
 
 #include "base/range.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
 #include "sim/eventq.hh"
 #include <map>
 #include <string>
+
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
 //
-class PhysicalMemory : public Memory
+class PhysicalMemory : public MemObject
 {
     class MemoryPort : public Port
     {
@@ -68,12 +69,8 @@ class PhysicalMemory : public Memory
         virtual int deviceBlockSize();
     };
 
-    std::map<std::string, MemoryPort*> memoryPortList;
-
     virtual Port * getPort(const char *if_name);
 
-    virtual Port * addPort(std::string portName);
-
     int numPorts;
 
     int lat;
diff --git a/mem/translating_port.hh b/mem/translating_port.hh
index acbc3fabc..2ba3d68e2 100644
--- a/mem/translating_port.hh
+++ b/mem/translating_port.hh
@@ -29,8 +29,6 @@
 #ifndef __MEM_TRANSLATING_PROT_HH__
 #define __MEM_TRANSLATING_PROT_HH__
 
-#include "mem/memory.hh"
-
 class Port;
 class PageTable;