diff options
| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-02-09 12:56:24 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-02-09 12:56:24 -0500 |
| commit | 230a5a608dfb2204e2886a795e6bd8a30224b84f (patch) | |
| tree | 81d312257237c4d13ad44836d55d2f192a479036 /objects/BaseCPU.mpy | |
| parent | d9317dd348f3acd853d1e6a09c09f2a27ad5d707 (diff) | |
| parent | c4089562d5add225cd8275b59456eb7eb559b988 (diff) | |
| download | gem5-230a5a608dfb2204e2886a795e6bd8a30224b84f.tar.xz | |
Merger
cpu/simple_cpu/simple_cpu.hh:
Merge
--HG--
extra : convert_revision : 1b6003ac731051fefacb7d7a30c317553b4bf1bc
Diffstat (limited to 'objects/BaseCPU.mpy')
| -rw-r--r-- | objects/BaseCPU.mpy | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy index 2aca9120d..f6e6ff96c 100644 --- a/objects/BaseCPU.mpy +++ b/objects/BaseCPU.mpy @@ -1,4 +1,5 @@ simobj BaseCPU(SimObject): + type = 'BaseCPU' abstract = True icache = Param.BaseMem(NULL, "L1 instruction cache object") dcache = Param.BaseMem(NULL, "L1 data cache object") @@ -18,7 +19,7 @@ simobj BaseCPU(SimObject): max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") - defer_registration = Param.Bool(false, + defer_registration = Param.Bool(False, "defer registration with system (for sampling)") def check(self): |