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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-02-09 12:56:24 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-02-09 12:56:24 -0500 |
| commit | 230a5a608dfb2204e2886a795e6bd8a30224b84f (patch) | |
| tree | 81d312257237c4d13ad44836d55d2f192a479036 /objects/IntrControl.mpy | |
| parent | d9317dd348f3acd853d1e6a09c09f2a27ad5d707 (diff) | |
| parent | c4089562d5add225cd8275b59456eb7eb559b988 (diff) | |
| download | gem5-230a5a608dfb2204e2886a795e6bd8a30224b84f.tar.xz | |
Merger
cpu/simple_cpu/simple_cpu.hh:
Merge
--HG--
extra : convert_revision : 1b6003ac731051fefacb7d7a30c317553b4bf1bc
Diffstat (limited to 'objects/IntrControl.mpy')
| -rw-r--r-- | objects/IntrControl.mpy | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy index 7c97746ff..1ef5a17ee 100644 --- a/objects/IntrControl.mpy +++ b/objects/IntrControl.mpy @@ -1,2 +1,3 @@ simobj IntrControl(SimObject): + type = 'IntrControl' cpu = Param.BaseCPU(Super, "the cpu") |