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authorKevin Lim <ktlim@umich.edu>2006-08-24 17:43:08 -0400
committerKevin Lim <ktlim@umich.edu>2006-08-24 17:43:08 -0400
commitad2fa1e1c9587e8c2a2b7f3e5a9c592312042eb4 (patch)
treee52b0443cc937e127c5d31b49f0c2dcf280c4d50 /python/m5/objects/AlphaFullCPU.py
parent74e8abd37ecd637a607f90e36aed1a3a16eea7da (diff)
downloadgem5-ad2fa1e1c9587e8c2a2b7f3e5a9c592312042eb4.tar.xz
Support profiling.
--HG-- extra : convert_revision : eab02dea68442bd3f8c5d1d16b7f93f43cbda2a5
Diffstat (limited to 'python/m5/objects/AlphaFullCPU.py')
-rw-r--r--python/m5/objects/AlphaFullCPU.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py
index 015e9d872..5b6fa1063 100644
--- a/python/m5/objects/AlphaFullCPU.py
+++ b/python/m5/objects/AlphaFullCPU.py
@@ -10,6 +10,8 @@ class DerivAlphaFullCPU(BaseCPU):
mem = Param.FunctionalMemory(NULL, "memory")
checker = Param.BaseCPU(NULL, "checker")
+ if build_env['FULL_SYSTEM']:
+ profile = Param.Latency('0ns', "trace the kernel stack")
cachePorts = Param.Unsigned("Cache Ports")