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| author | Kevin Lim <ktlim@umich.edu> | 2005-03-14 15:40:51 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2005-03-14 15:40:51 -0500 |
| commit | 8f2a84cbe5a0cd26053d49fb0376ec18bcbeb8f4 (patch) | |
| tree | 1b707750f5064ed9f89a4a1ecc2f2be4d3daddc0 /python/m5/objects/BaseCPU.mpy | |
| parent | c12a665c3120b61ed4e09da5d8a52c57406763d5 (diff) | |
| parent | 76e6dd01ae4a534adad1d34398fefc819771a781 (diff) | |
| download | gem5-8f2a84cbe5a0cd26053d49fb0376ec18bcbeb8f4.tar.xz | |
Merge
--HG--
extra : convert_revision : 22919164108afd74f30207606f59a38992991dae
Diffstat (limited to 'python/m5/objects/BaseCPU.mpy')
| -rw-r--r-- | python/m5/objects/BaseCPU.mpy | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy new file mode 100644 index 000000000..5d8305d88 --- /dev/null +++ b/python/m5/objects/BaseCPU.mpy @@ -0,0 +1,25 @@ +simobj BaseCPU(SimObject): + type = 'BaseCPU' + abstract = True + icache = Param.BaseMem(NULL, "L1 instruction cache object") + dcache = Param.BaseMem(NULL, "L1 data cache object") + + if build_env['FULL_SYSTEM']: + dtb = Param.AlphaDTB("Data TLB") + itb = Param.AlphaITB("Instruction TLB") + mem = Param.FunctionalMemory("memory") + system = Param.BaseSystem(Super, "system object") + else: + workload = VectorParam.Process("processes to run") + + max_insts_all_threads = Param.Counter(0, + "terminate when all threads have reached this inst count") + max_insts_any_thread = Param.Counter(0, + "terminate when any thread reaches this inst count") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + + defer_registration = Param.Bool(False, + "defer registration with system (for sampling)") |