Major cleanup of python config code.

Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76

1 files changed, 0 insertions, 64 deletions

diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy
deleted file mode 100644
index a9a665f77..000000000
--- a/python/m5/objects/BaseCache.mpy
+++ /dev/null
@@ -1,64 +0,0 @@
-from BaseMem import BaseMem
-
-class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
-
-simobj BaseCache(BaseMem):
-    type = 'BaseCache'
-    adaptive_compression = Param.Bool(False,
-        "Use an adaptive compression scheme")
-    assoc = Param.Int("associativity")
-    block_size = Param.Int("block size in bytes")
-    compressed_bus = Param.Bool(False,
-        "This cache connects to a compressed memory")
-    compression_latency = Param.Latency('0c',
-        "Latency in cycles of compression algorithm")
-    do_copy = Param.Bool(False, "perform fast copies in the cache")
-    hash_delay = Param.Int(1, "time in cycles of hash access")
-    in_bus = Param.Bus(NULL, "incoming bus object")
-    lifo = Param.Bool(False,
-        "whether this NIC partition should use LIFO repl. policy")
-    max_miss_count = Param.Counter(0,
-        "number of misses to handle before calling exit")
-    mem_trace = Param.MemTraceWriter(NULL,
-                                     "memory trace writer to record accesses")
-    mshrs = Param.Int("number of MSHRs (max outstanding requests)")
-    out_bus = Param.Bus("outgoing bus object")
-    prioritizeRequests = Param.Bool(False,
-        "always service demand misses first")
-    protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
-    repl = Param.Repl(NULL, "replacement policy")
-    size = Param.MemorySize("capacity in bytes")
-    split = Param.Bool(False, "whether or not this cache is split")
-    split_size = Param.Int(0,
-        "How many ways of the cache belong to CPU/LRU partition")
-    store_compressed = Param.Bool(False,
-        "Store compressed data in the cache")
-    subblock_size = Param.Int(0,
-        "Size of subblock in IIC used for compression")
-    tgts_per_mshr = Param.Int("max number of accesses per MSHR")
-    trace_addr = Param.Addr(0, "address to trace")
-    two_queue = Param.Bool(False,
-        "whether the lifo should have two queue replacement")
-    write_buffers = Param.Int(8, "number of write buffers")
-    prefetch_miss = Param.Bool(False,
-         "wheter you are using the hardware prefetcher from Miss stream")
-    prefetch_access = Param.Bool(False,
-         "wheter you are using the hardware prefetcher from Access stream")
-    prefetcher_size = Param.Int(100,
-         "Number of entries in the harware prefetch queue")
-    prefetch_past_page = Param.Bool(False,
-         "Allow prefetches to cross virtual page boundaries")
-    prefetch_serial_squash = Param.Bool(False,
-         "Squash prefetches with a later time on a subsequent miss")
-    prefetch_degree = Param.Int(1,
-         "Degree of the prefetch depth")
-    prefetch_latency = Param.Tick(10,
-         "Latency of the prefetcher")
-    prefetch_policy = Param.Prefetch('none',
-         "Type of prefetcher to use")
-    prefetch_cache_check_push = Param.Bool(True,
-         "Check if in cash on push or pop of prefetch queue")
-    prefetch_use_cpu_id = Param.Bool(True,
-         "Use the CPU ID to seperate calculations of prefetches")
-    prefetch_data_accesses_only = Param.Bool(False,
-         "Only prefetch on data not on instruction accesses")