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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-16 00:40:48 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-16 00:40:48 -0500 |
| commit | c8538d6a7e2b58ebcbe567023c9e1c5a0c3ee5a6 (patch) | |
| tree | a25c84a48af9185b06f5166ac386f8cedcdf3e3d /python/m5/objects/Device.mpy | |
| parent | 42753edb3c93cbc2ef7a6698b88b20bd641122fe (diff) | |
| download | gem5-c8538d6a7e2b58ebcbe567023c9e1c5a0c3ee5a6.tar.xz | |
Enhancements to python config proxy class.
python/m5/config.py:
- Enhanced Proxy class now supports subscripting, e.g.,
parent.cpu[0] or even parent.cpu[0].icache.
- Proxy also supports multiplication (e.g., parent.cycle * 3),
though this feature has not been tested.
- Subscript 0 works even on non-lists, so you can safely say
cpu[0] and get the first cpu even if there's only one.
- Changed name of proxy object from 'Super' to 'parent', and
changed "wild card" notation from plain 'Super' to 'parent.any'.
python/m5/objects/AlphaConsole.mpy:
python/m5/objects/BaseCPU.mpy:
python/m5/objects/BaseSystem.mpy:
python/m5/objects/Device.mpy:
python/m5/objects/Ethernet.mpy:
python/m5/objects/Ide.mpy:
python/m5/objects/IntrControl.mpy:
python/m5/objects/Pci.mpy:
python/m5/objects/PhysicalMemory.mpy:
python/m5/objects/Platform.mpy:
python/m5/objects/SimConsole.mpy:
python/m5/objects/SimpleDisk.mpy:
python/m5/objects/Tsunami.mpy:
python/m5/objects/Uart.mpy:
Change 'Super.foo' to 'parent.foo' (and 'Super' to 'parent.any').
--HG--
extra : convert_revision : f996d0a3366d5e3e60ae5973691148c3d7cd497d
Diffstat (limited to 'python/m5/objects/Device.mpy')
| -rw-r--r-- | python/m5/objects/Device.mpy | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/python/m5/objects/Device.mpy b/python/m5/objects/Device.mpy index 47f8db1cb..a0d02a647 100644 --- a/python/m5/objects/Device.mpy +++ b/python/m5/objects/Device.mpy @@ -14,7 +14,7 @@ simobj FooPioDevice(FunctionalMemory): type = 'PioDevice' abstract = True addr = Param.Addr("Device Address") - mmu = Param.MemoryController(Super, "Memory Controller") + mmu = Param.MemoryController(parent.any, "Memory Controller") io_bus = Param.Bus(NULL, "The IO Bus to attach to") pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") @@ -25,7 +25,7 @@ simobj FooDmaDevice(FooPioDevice): simobj PioDevice(FooPioDevice): type = 'PioDevice' abstract = True - platform = Param.Platform(Super, "Platform") + platform = Param.Platform(parent.any, "Platform") simobj DmaDevice(PioDevice): type = 'DmaDevice' |