summaryrefslogtreecommitdiff
path: root/python/m5/objects/Device.py
diff options
context:
space:
mode:
authorNathan Binkert <binkertn@umich.edu>2005-11-20 16:57:53 -0500
committerNathan Binkert <binkertn@umich.edu>2005-11-20 16:57:53 -0500
commit12d903a650a91798eae2389e70f7d4471d130919 (patch)
tree625b9e1a80405e63298e00aa12855231f502ab06 /python/m5/objects/Device.py
parentccae5838fd4ec3b6aa27024beb24e231f6d3c63a (diff)
downloadgem5-12d903a650a91798eae2389e70f7d4471d130919.tar.xz
io_bus is split out into pio_bus and dma_bus so that any device
can specify either independently. python/m5/objects/Device.py: io_bus is split out into pio_bus and dma_bus so that any device can specify either independently. dma_bus defaults to point to whatever pio_bus uses. --HG-- extra : convert_revision : d35d5374d0bf592f6b5df465c05203577b8b8763
Diffstat (limited to 'python/m5/objects/Device.py')
-rw-r--r--python/m5/objects/Device.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py
index 7f6ccd3e7..d7ca014a9 100644
--- a/python/m5/objects/Device.py
+++ b/python/m5/objects/Device.py
@@ -16,12 +16,13 @@ class FooPioDevice(FunctionalMemory):
abstract = True
addr = Param.Addr("Device Address")
mmu = Param.MemoryController(Parent.any, "Memory Controller")
- io_bus = Param.Bus(NULL, "The IO Bus to attach to")
+ pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
class FooDmaDevice(FooPioDevice):
type = 'DmaDevice'
abstract = True
+ dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
class PioDevice(FooPioDevice):
type = 'PioDevice'
@@ -31,4 +32,4 @@ class PioDevice(FooPioDevice):
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
-
+ dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")