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authorGabe Black <gblack@eecs.umich.edu>2006-02-20 23:55:25 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-20 23:55:25 -0500
commit74d7cd1ceadd8ba803bbb83750e11a3c488d3fe1 (patch)
treebb1cfdce0b5c1d2b0acef8d38c08b15d49616327 /python/m5/objects/Ethernet.py
parent466284b5d29ad0d44c1b020353cf7521be2b90de (diff)
parent3a0102536bdbf00629e6ba944bd55ee0ec77fb52 (diff)
downloadgem5-74d7cd1ceadd8ba803bbb83750e11a3c488d3fe1.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : da72b3593037c2a67a56c799e292853b8aece907
Diffstat (limited to 'python/m5/objects/Ethernet.py')
-rw-r--r--python/m5/objects/Ethernet.py1
1 files changed, 0 insertions, 1 deletions
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index f58ece0be..3a7f88d04 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -76,7 +76,6 @@ class EtherDevBase(PciDevice):
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
- pio_delay_write = Param.Bool(False, "Delay pio writes until timing occurs")
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")