Major cleanup of python config code.

Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions.  This commit is for my
own convenience and won't be pushed until more testing
is done.

python/m5/__init__.py:
    Get rid of mpy_importer and param_types.
python/m5/config.py:
    Major cleanup.  We now have separate classes and
    instances for SimObjects.  Proxy handling and param
    conversion significantly reorganized.  No explicit
    instantiation step anymore; we can dump an ini file
    straight from the original tree.
    Still needs more/better/truer comments.
test/genini.py:
    Replace LoadMpyFile() with built-in execfile().
    Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
    Fixes for eliminating mpy_importer, and modified
    handling of frequency/latency params.
    Also renamed parent to Parent.

--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76

1 files changed, 122 insertions, 0 deletions

diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
new file mode 100644
index 000000000..69dec1528
--- /dev/null
+++ b/python/m5/objects/Ethernet.py
@@ -0,0 +1,122 @@
+from m5 import *
+from Device import DmaDevice
+from Pci import PciDevice
+
+class EtherInt(SimObject):
+    type = 'EtherInt'
+    abstract = True
+    peer = Param.EtherInt(NULL, "peer interface")
+
+class EtherLink(SimObject):
+    type = 'EtherLink'
+    int1 = Param.EtherInt("interface 1")
+    int2 = Param.EtherInt("interface 2")
+    delay = Param.Latency('0us', "packet transmit delay")
+    speed = Param.NetworkBandwidth('100Mbps', "link speed")
+    dump = Param.EtherDump(NULL, "dump object")
+
+class EtherBus(SimObject):
+    type = 'EtherBus'
+    loopback = Param.Bool(True, "send packet back to the sending interface")
+    dump = Param.EtherDump(NULL, "dump object")
+    speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
+
+class EtherTap(EtherInt):
+    type = 'EtherTap'
+    bufsz = Param.Int(10000, "tap buffer size")
+    dump = Param.EtherDump(NULL, "dump object")
+    port = Param.UInt16(3500, "tap port")
+
+class EtherDump(SimObject):
+    type = 'EtherDump'
+    file = Param.String("dump file")
+
+class EtherDev(DmaDevice):
+    type = 'EtherDev'
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
+
+    dma_data_free = Param.Bool(False, "DMA of Data is free")
+    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
+    rx_delay = Param.Latency('1us', "Receive Delay")
+    tx_delay = Param.Latency('1us', "Transmit Delay")
+
+    intr_delay = Param.Latency('0us', "Interrupt Delay")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+    tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
+
+class NSGigE(PciDevice):
+    type = 'NSGigE'
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
+
+    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
+    dma_data_free = Param.Bool(False, "DMA of Data is free")
+    dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+
+
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
+    rx_delay = Param.Latency('1us', "Receive Delay")
+    tx_delay = Param.Latency('1us', "Transmit Delay")
+
+    rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
+    tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
+
+    m5reg = Param.UInt32(0, "Register for m5 usage")
+
+    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+
+class EtherDevInt(EtherInt):
+    type = 'EtherDevInt'
+    device = Param.EtherDev("Ethernet device of this interface")
+
+class NSGigEInt(EtherInt):
+    type = 'NSGigEInt'
+    device = Param.NSGigE("Ethernet device of this interface")
+
+class Sinic(PciDevice):
+    type = 'Sinic'
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
+
+    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
+    dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+    dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+    dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+    dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+
+    rx_filter = Param.Bool(True, "Enable Receive Filter")
+    rx_delay = Param.Latency('1us', "Receive Delay")
+    tx_delay = Param.Latency('1us', "Transmit Delay")
+
+    rx_max_copy = Param.MemorySize('16kB', "rx max copy")
+    tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+    rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
+    tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
+    rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
+    tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
+
+    intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
+    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+
+class SinicInt(EtherInt):
+    type = 'SinicInt'
+    device = Param.Sinic("Ethernet device of this interface")