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| author | Nathan Binkert <binkertn@umich.edu> | 2005-03-11 18:32:36 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2005-03-11 18:32:36 -0500 |
| commit | e6902a907e333c09d64d520f4c978edf7e098f6a (patch) | |
| tree | 5b0acd0444285290365fbead19f081b8f3ebdd9a /python/m5/objects/Pci.mpy | |
| parent | b1f41a7aa0f617014d2bf6d5d3675830ffac213c (diff) | |
| parent | fa1650a08e56b176c2b31cd5c3b8939820e93884 (diff) | |
| download | gem5-e6902a907e333c09d64d520f4c978edf7e098f6a.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into ziff.eecs.umich.edu:/z/binkertn/research/m5/current
--HG--
extra : convert_revision : abc24d21097770ad323a2c0d537d3e9424db0d7d
Diffstat (limited to 'python/m5/objects/Pci.mpy')
| -rw-r--r-- | python/m5/objects/Pci.mpy | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/python/m5/objects/Pci.mpy b/python/m5/objects/Pci.mpy new file mode 100644 index 000000000..caa3c52ff --- /dev/null +++ b/python/m5/objects/Pci.mpy @@ -0,0 +1,52 @@ +from Device import FooPioDevice, DmaDevice + +simobj PciConfigData(FooPioDevice): + type = 'PciConfigData' + addr = 0xffffffffffffffffL + VendorID = Param.UInt16("Vendor ID") + DeviceID = Param.UInt16("Device ID") + Command = Param.UInt16(0, "Command") + Status = Param.UInt16(0, "Status") + Revision = Param.UInt8(0, "Device") + ProgIF = Param.UInt8(0, "Programming Interface") + SubClassCode = Param.UInt8(0, "Sub-Class Code") + ClassCode = Param.UInt8(0, "Class Code") + CacheLineSize = Param.UInt8(0, "System Cacheline Size") + LatencyTimer = Param.UInt8(0, "PCI Latency Timer") + HeaderType = Param.UInt8(0, "PCI Header Type") + BIST = Param.UInt8(0, "Built In Self Test") + + BAR0 = Param.UInt32(0x00, "Base Address Register 0") + BAR1 = Param.UInt32(0x00, "Base Address Register 1") + BAR2 = Param.UInt32(0x00, "Base Address Register 2") + BAR3 = Param.UInt32(0x00, "Base Address Register 3") + BAR4 = Param.UInt32(0x00, "Base Address Register 4") + BAR5 = Param.UInt32(0x00, "Base Address Register 5") + BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") + BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") + BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") + BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") + BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") + BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") + + CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") + SubsystemID = Param.UInt16(0x00, "Subsystem ID") + SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") + ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") + InterruptLine = Param.UInt8(0x00, "Interrupt Line") + InterruptPin = Param.UInt8(0x00, "Interrupt Pin") + MaximumLatency = Param.UInt8(0x00, "Maximum Latency") + MinimumGrant = Param.UInt8(0x00, "Minimum Grant") + +simobj PciConfigAll(FooPioDevice): + type = 'PciConfigAll' + +simobj PciDevice(DmaDevice): + type = 'PciDevice' + abstract = True + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + configdata = Param.PciConfigData(Super, "PCI Config data") + configspace = Param.PciConfigAll(Super, "PCI Configspace") + addr = 0xffffffffffffffffL |