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authorBenjamin Nash <benash@umich.edu>2005-07-26 12:28:33 -0400
committerBenjamin Nash <benash@umich.edu>2005-07-26 12:28:33 -0400
commit6e0ad62fdc8c0518e54366e3bca25e75335f3198 (patch)
treef594828e38b1668ac55c6716564f8ac4955ae8fa /python/m5/objects/Pci.py
parent32b52fe7126091692c0a76314bb3692fa3f70d27 (diff)
downloadgem5-6e0ad62fdc8c0518e54366e3bca25e75335f3198.tar.xz
Various changes to I/O, addition of PciFake device to improve FreeBSD compatibility.
SConscript: Include pcifake.cc, fix spacing. dev/ide_ctrl.cc: Consolidate switch-case blocks. dev/ide_disk.cc: Add comments. dev/pciconfigall.cc: Adjust spacing. dev/pcidev.cc: Adjust spacing, rearrange code. dev/tsunami_io.cc: Rearrange code. dev/uart8250.cc: Switch uart interrupt interval back to original value. python/m5/objects/Pci.py: Add PciFake class to be used as a PCI-ISA bridge device. --HG-- extra : convert_revision : 8aea94318510079a310377f297aa161ba5f7864c
Diffstat (limited to 'python/m5/objects/Pci.py')
-rw-r--r--python/m5/objects/Pci.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
index 0957e2883..defdd10a3 100644
--- a/python/m5/objects/Pci.py
+++ b/python/m5/objects/Pci.py
@@ -50,3 +50,6 @@ class PciDevice(DmaDevice):
pci_func = Param.Int("PCI function code")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
+
+class PciFake(PciDevice):
+ type = 'PciFake'