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author | Steve Reinhardt <stever@eecs.umich.edu> | 2005-05-29 01:14:50 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2005-05-29 01:14:50 -0400 |
commit | aad02f80880c1b88b8f4feaa605653953848b7c3 (patch) | |
tree | 5128713ff5557e579d05c950c5a40bc9900f8f79 /python/m5/objects/Pci.py | |
parent | ef5a7d91a5233521e82c68b1bace70852eda1ea4 (diff) | |
download | gem5-aad02f80880c1b88b8f4feaa605653953848b7c3.tar.xz |
Major cleanup of python config code.
Special mpy importer is gone; everything is just plain
Python now (funky, but straight-up).
May not completely work yet... generates identical ini
files for many configs/kernel settings, but I have yet
to run it against regressions. This commit is for my
own convenience and won't be pushed until more testing
is done.
python/m5/__init__.py:
Get rid of mpy_importer and param_types.
python/m5/config.py:
Major cleanup. We now have separate classes and
instances for SimObjects. Proxy handling and param
conversion significantly reorganized. No explicit
instantiation step anymore; we can dump an ini file
straight from the original tree.
Still needs more/better/truer comments.
test/genini.py:
Replace LoadMpyFile() with built-in execfile().
Export __main__.m5_build_env.
python/m5/objects/AlphaConsole.py:
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/AlphaTLB.py:
python/m5/objects/BadDevice.py:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/CoherenceProtocol.py:
python/m5/objects/Device.py:
python/m5/objects/DiskImage.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Ide.py:
python/m5/objects/IntrControl.py:
python/m5/objects/MemTest.py:
python/m5/objects/Pci.py:
python/m5/objects/PhysicalMemory.py:
python/m5/objects/Platform.py:
python/m5/objects/Process.py:
python/m5/objects/Repl.py:
python/m5/objects/Root.py:
python/m5/objects/SimConsole.py:
python/m5/objects/SimpleDisk.py:
python/m5/objects/Tsunami.py:
python/m5/objects/Uart.py:
Fixes for eliminating mpy_importer, and modified
handling of frequency/latency params.
Also renamed parent to Parent.
--HG--
rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py
rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py
rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py
rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py
rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py
rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py
rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py
rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py
extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
Diffstat (limited to 'python/m5/objects/Pci.py')
-rw-r--r-- | python/m5/objects/Pci.py | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py new file mode 100644 index 000000000..0957e2883 --- /dev/null +++ b/python/m5/objects/Pci.py @@ -0,0 +1,52 @@ +from m5 import * +from Device import FooPioDevice, DmaDevice + +class PciConfigData(SimObject): + type = 'PciConfigData' + VendorID = Param.UInt16("Vendor ID") + DeviceID = Param.UInt16("Device ID") + Command = Param.UInt16(0, "Command") + Status = Param.UInt16(0, "Status") + Revision = Param.UInt8(0, "Device") + ProgIF = Param.UInt8(0, "Programming Interface") + SubClassCode = Param.UInt8(0, "Sub-Class Code") + ClassCode = Param.UInt8(0, "Class Code") + CacheLineSize = Param.UInt8(0, "System Cacheline Size") + LatencyTimer = Param.UInt8(0, "PCI Latency Timer") + HeaderType = Param.UInt8(0, "PCI Header Type") + BIST = Param.UInt8(0, "Built In Self Test") + + BAR0 = Param.UInt32(0x00, "Base Address Register 0") + BAR1 = Param.UInt32(0x00, "Base Address Register 1") + BAR2 = Param.UInt32(0x00, "Base Address Register 2") + BAR3 = Param.UInt32(0x00, "Base Address Register 3") + BAR4 = Param.UInt32(0x00, "Base Address Register 4") + BAR5 = Param.UInt32(0x00, "Base Address Register 5") + BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") + BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") + BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") + BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") + BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") + BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") + + CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") + SubsystemID = Param.UInt16(0x00, "Subsystem ID") + SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") + ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") + InterruptLine = Param.UInt8(0x00, "Interrupt Line") + InterruptPin = Param.UInt8(0x00, "Interrupt Pin") + MaximumLatency = Param.UInt8(0x00, "Maximum Latency") + MinimumGrant = Param.UInt8(0x00, "Minimum Grant") + +class PciConfigAll(FooPioDevice): + type = 'PciConfigAll' + +class PciDevice(DmaDevice): + type = 'PciDevice' + abstract = True + addr = 0xffffffffL + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + configdata = Param.PciConfigData(Parent.any, "PCI Config data") + configspace = Param.PciConfigAll(Parent.any, "PCI Configspace") |