diff options
| author | Kevin Lim <ktlim@umich.edu> | 2005-03-28 14:40:02 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2005-03-28 14:40:02 -0500 |
| commit | 2e2d9b5c35a8bc1f5b8f1a96cd9712429475b1d0 (patch) | |
| tree | 5700b3d927c17ffdd3b8c53d1209e18f8be26fd1 /python/m5/objects | |
| parent | 2ec918362ee1235cf0d36fb7aac3e3f4ce2d4ddc (diff) | |
| parent | a86b95cb182b435bda5d76197cd9f32ba6db83c2 (diff) | |
| download | gem5-2e2d9b5c35a8bc1f5b8f1a96cd9712429475b1d0.tar.xz | |
Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5
--HG--
extra : convert_revision : 95e94251150a3eea380b6b3bc3a9596e188df315
Diffstat (limited to 'python/m5/objects')
| -rw-r--r-- | python/m5/objects/BaseCache.mpy | 2 | ||||
| -rw-r--r-- | python/m5/objects/Bus.mpy | 2 | ||||
| -rw-r--r-- | python/m5/objects/Ethernet.mpy | 4 | ||||
| -rw-r--r-- | python/m5/objects/Root.mpy | 2 |
4 files changed, 5 insertions, 5 deletions
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index 98a422e30..b9986917f 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -23,7 +23,7 @@ simobj BaseCache(BaseMem): "always service demand misses first") protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") repl = Param.Repl(NULL, "replacement policy") - size = Param.Int("capacity in bytes") + size = Param.MemorySize("capacity in bytes") split = Param.Bool(False, "whether or not this cache is split") split_size = Param.Int(0, "How many ways of the cache belong to CPU/LRU partition") diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy index 025d69785..aa12f757a 100644 --- a/python/m5/objects/Bus.mpy +++ b/python/m5/objects/Bus.mpy @@ -2,5 +2,5 @@ from BaseHier import BaseHier simobj Bus(BaseHier): type = 'Bus' - clock_ratio = Param.Int("ratio of CPU to bus frequency") + clock_ratio = Param.ClockPeriod("ratio of CPU to bus frequency") width = Param.Int("bus width in bytes") diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy index cd251f36d..3acd8d04d 100644 --- a/python/m5/objects/Ethernet.mpy +++ b/python/m5/objects/Ethernet.mpy @@ -68,8 +68,8 @@ simobj NSGigE(PciDevice): rx_delay = Param.Tick(1000, "Receive Delay") tx_delay = Param.Tick(1000, "Transmit Delay") - rx_fifo_size = Param.Int(131072, "max size in bytes of rxFifo") - tx_fifo_size = Param.Int(131072, "max size in bytes of txFifo") + rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo") + tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo") intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy index 0e531054b..c535bd2dc 100644 --- a/python/m5/objects/Root.mpy +++ b/python/m5/objects/Root.mpy @@ -5,7 +5,7 @@ from Trace import Trace simobj Root(SimObject): type = 'Root' - frequency = Param.Tick(200000000, "tick frequency") + frequency = Param.RootFrequency('200MHz', "tick frequency") output_file = Param.String('cout', "file to dump simulator output to") full_system = Param.Bool("Full system simulation?") hier = HierParams(do_data = False, do_events = True) |