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| author | Ali Saidi <saidi@eecs.umich.edu> | 2005-03-14 15:38:26 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2005-03-14 15:38:26 -0500 |
| commit | 76e6dd01ae4a534adad1d34398fefc819771a781 (patch) | |
| tree | a678ca355625b9199cbb0f64ca42d247e520accb /python/m5/objects | |
| parent | c1f5b983f0c8cece7a8387b05b40889c9520fb39 (diff) | |
| parent | bc2923f78d739ad5ff42dee402c5ba27c02004f1 (diff) | |
| download | gem5-76e6dd01ae4a534adad1d34398fefc819771a781.tar.xz | |
Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5
--HG--
extra : convert_revision : 9eed6f31249ff099464044b32b882b3cc041b57a
Diffstat (limited to 'python/m5/objects')
| -rw-r--r-- | python/m5/objects/BaseCPU.mpy | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy index be93e8ad1..5d8305d88 100644 --- a/python/m5/objects/BaseCPU.mpy +++ b/python/m5/objects/BaseCPU.mpy @@ -4,7 +4,7 @@ simobj BaseCPU(SimObject): icache = Param.BaseMem(NULL, "L1 instruction cache object") dcache = Param.BaseMem(NULL, "L1 data cache object") - if env.get('FULL_SYSTEM', 'False'): + if build_env['FULL_SYSTEM']: dtb = Param.AlphaDTB("Data TLB") itb = Param.AlphaITB("Instruction TLB") mem = Param.FunctionalMemory("memory") |