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authorNathan Binkert <binkertn@umich.edu>2006-02-20 23:41:50 -0500
committerNathan Binkert <binkertn@umich.edu>2006-02-20 23:41:50 -0500
commit3a0102536bdbf00629e6ba944bd55ee0ec77fb52 (patch)
tree125bebe1771dbf336f7830a030ab39fc67ae9e9f /python/m5/objects
parent7c642b710679f01d4ec43e6562dd854180dd8c41 (diff)
downloadgem5-3a0102536bdbf00629e6ba944bd55ee0ec77fb52.tar.xz
Get rid of the code that delays PIO write accesses
until the cache access occurs. The fundamental problem is that a subsequent read that occurs functionally will get a functionally incorrect result that can break driver code. dev/ns_gige.cc: dev/ns_gige.hh: dev/sinic.cc: dev/sinic.hh: get rid of pio_delay write and the associated code to move the write to the cache access function dev/sinicreg.hh: no more write delays python/m5/objects/Ethernet.py: get rid of pio_delay write --HG-- extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d
Diffstat (limited to 'python/m5/objects')
-rw-r--r--python/m5/objects/Ethernet.py1
1 files changed, 0 insertions, 1 deletions
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index f58ece0be..3a7f88d04 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -76,7 +76,6 @@ class EtherDevBase(PciDevice):
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
- pio_delay_write = Param.Bool(False, "Delay pio writes until timing occurs")
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")