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authorAli Saidi <saidi@eecs.umich.edu>2006-03-25 18:31:20 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-25 18:31:20 -0500
commitb38f67d5b7ad9c2f5ff7580e20fb86c4a877589d (patch)
tree861137c79bf858c09f63d71b51494cc9c3b043a7 /python/m5/objects
parenta70ce910f3303efe934c564817cc421369f51b36 (diff)
downloadgem5-b38f67d5b7ad9c2f5ff7580e20fb86c4a877589d.tar.xz
Implement a very very simple bus
requestTime -> time responseTime -> packet.time Make CPU and memory able to connect to the bus dev/io_device.cc: update for request and packet both having a time hand platform off to port for eventual selection of request modes dev/io_device.hh: update for request and packet both havig a time hand platform off to port for eventual selection of request modes mem/bus.hh: Add a device map struct that maps a range to a portId - Which needs work it theory it should be an interval tree - but it is a list and works fine right now Add a function called findPort which returns port for an addr range Add a deviceBlockSize function that really shouldn't exist, but it was easier than fixing the translating port mem/packet.hh: add a time to each packet mem/physical.cc: mem/physical.hh: python/m5/objects/PhysicalMemory.py: Make physical memory take a MemObject parameter of what to connect to mem/request.hh: remove requestTime/responseTime for just time in request which is requset time and the time in the packet which is responsetime python/m5/objects/BaseCPU.py: Instead of memory cpu connects to any memory object python/m5/objects/Bus.py: Fix for new bus object --HG-- extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
Diffstat (limited to 'python/m5/objects')
-rw-r--r--python/m5/objects/BaseCPU.py2
-rw-r--r--python/m5/objects/Bus.py7
-rw-r--r--python/m5/objects/PhysicalMemory.py1
3 files changed, 5 insertions, 5 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index 07cb850f1..fccddb1ec 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -9,7 +9,7 @@ class BaseCPU(SimObject):
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
else:
- mem = Param.Memory(Parent.any, "memory")
+ mem = Param.MemObject("memory")
workload = VectorParam.Process("processes to run")
max_insts_all_threads = Param.Counter(0,
diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py
index 26509d7d2..8c5397281 100644
--- a/python/m5/objects/Bus.py
+++ b/python/m5/objects/Bus.py
@@ -1,7 +1,6 @@
from m5 import *
-from BaseHier import BaseHier
+from MemObject import MemObject
-class Bus(BaseHier):
+class Bus(MemObject):
type = 'Bus'
- clock = Param.Clock("bus frequency")
- width = Param.Int("bus width in bytes")
+ bus_id = Param.Int(0, "blah")
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py
index b0aba1a7d..7c5a0c517 100644
--- a/python/m5/objects/PhysicalMemory.py
+++ b/python/m5/objects/PhysicalMemory.py
@@ -5,5 +5,6 @@ class PhysicalMemory(Memory):
type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
+ bus = Param.MemObject("Bus to attach to")
if build_env['FULL_SYSTEM']:
mmu = Param.MemoryController(Parent.any, "Memory Controller")