diff options
| author | Miguel Serrano <mserrano@umich.edu> | 2005-07-01 15:12:09 -0400 |
|---|---|---|
| committer | Miguel Serrano <mserrano@umich.edu> | 2005-07-01 15:12:09 -0400 |
| commit | 4f2480a18bdf98792e2ebf3471ce7cd3109ef824 (patch) | |
| tree | b2d8d27e41eae3d659dbe6e6665436d02bcea429 /python/m5/objects | |
| parent | 16a2357e8637fed706a94ab0da6226df8a2e7f07 (diff) | |
| parent | efd0c5d4b04f630f1b591af509458224b6d98655 (diff) | |
| download | gem5-4f2480a18bdf98792e2ebf3471ce7cd3109ef824.tar.xz | |
Merge m5read@m5.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/.automount/fox/y/mserrano/m5_new/m5
--HG--
extra : convert_revision : bb3e977e79599c459fb32f309ce5b486f1639afa
Diffstat (limited to 'python/m5/objects')
| -rw-r--r-- | python/m5/objects/AlphaConsole.py | 1 | ||||
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 1 | ||||
| -rw-r--r-- | python/m5/objects/Ethernet.py | 2 |
3 files changed, 2 insertions, 2 deletions
diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py index 32a137bec..f8f034682 100644 --- a/python/m5/objects/AlphaConsole.py +++ b/python/m5/objects/AlphaConsole.py @@ -5,6 +5,5 @@ class AlphaConsole(PioDevice): type = 'AlphaConsole' cpu = Param.BaseCPU(Parent.any, "Processor") disk = Param.SimpleDisk("Simple Disk") - num_cpus = Param.Int(1, "Number of CPUs") sim_console = Param.SimConsole(Parent.any, "The Simulator Console") system = Param.System(Parent.any, "system object") diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index 452b97c84..a90203729 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -10,6 +10,7 @@ class BaseCPU(SimObject): itb = Param.AlphaITB("Instruction TLB") mem = Param.FunctionalMemory("memory") system = Param.System(Parent.any, "system object") + cpu_id = Param.Int(-1, "CPU identifier") else: workload = VectorParam.Process("processes to run") diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 2fbfb1138..a357ba346 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -64,7 +64,7 @@ class NSGigE(PciDevice): hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") - clock = Param.Clock('100MHz', "State machine processor frequency") + clock = Param.Clock('0ns', "State machine processor frequency") dma_data_free = Param.Bool(False, "DMA of Data is free") dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") |