diff options
| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-23 17:02:34 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-23 17:02:34 -0500 |
| commit | b6247c9ea7ddc459a076dddf5e5f330da0211c1e (patch) | |
| tree | 1172ed1b9d52639378ca15be2e24f442c687f1e9 /python/m5/objects | |
| parent | 8fc06589cbf28b2a5bf13384d1c683dc50f68a8a (diff) | |
| download | gem5-b6247c9ea7ddc459a076dddf5e5f330da0211c1e.tar.xz | |
Add support for multiple ports on the memory. Hook up simple cpu to memory.
Ready to start testing if I could fix the linking errors I can't ever seem to fix.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add connecting of ports until builder can handle it.
mem/physical.cc:
Add function to allocate a port in the object
Remove some full_sys stuff untill needed
mem/physical.hh:
Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
Update the params
sim/process.cc:
Make sure to use the right name (hopefully CPU constructor already called)
--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
Diffstat (limited to 'python/m5/objects')
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index a90203729..fac452285 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -8,10 +8,10 @@ class BaseCPU(SimObject): if build_env['FULL_SYSTEM']: dtb = Param.AlphaDTB("Data TLB") itb = Param.AlphaITB("Instruction TLB") - mem = Param.FunctionalMemory("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") else: + mem = Param.Memory("memory") workload = VectorParam.Process("processes to run") max_insts_all_threads = Param.Counter(0, |