summaryrefslogtreecommitdiff
path: root/python/m5
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2006-05-12 18:16:07 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-05-12 18:16:07 -0400
commit03a00e5d32411f467735b2af890c1ca54930e949 (patch)
tree4154e4703c0c3e18bd4d6b4de98fe8650d6f704d /python/m5
parenta91ee5abc2275709871b016d43ca2d2440fa5000 (diff)
parent7929b9ee19b6fabc7e69b704fa07fdb6daa35c70 (diff)
downloadgem5-03a00e5d32411f467735b2af890c1ca54930e949.tar.xz
Merge zeep.pool:/z/saidi/work/m5.head
into zeep.pool:/z/saidi/work/m5.nm_m5_pull SConscript: dram memory needs to be converted to newmem before we can use it dev/ide_ctrl.cc: don't need this printing in newmem dev/ide_disk.cc: will read stats in next commit dev/sinic.cc: merge sinic from head, still needs work --HG-- extra : convert_revision : b9aabd8c7814d07d54ce6f971aad3ec349fa24e1
Diffstat (limited to 'python/m5')
-rw-r--r--python/m5/objects/Ethernet.py10
1 files changed, 8 insertions, 2 deletions
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 0667fc6d7..4286c71c8 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -101,8 +101,14 @@ class Sinic(EtherDevBase):
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
- rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
- tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
+ rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
+ rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
+ tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
+ tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
+ virtual_count = Param.UInt32(1, "Virtualized SINIC")
+ zero_copy = Param.Bool(False, "Zero copy receive")
+ delay_copy = Param.Bool(False, "Delayed copy transmit")
+ virtual_addr = Param.Bool(False, "Virtual addressing")
class SinicInt(EtherInt):
type = 'SinicInt'