Standardize clock parameter names to 'clock'.

Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506

7 files changed, 72 insertions, 55 deletions

diff --git a/python/m5/config.py b/python/m5/config.py
index 0aac595b1..f7b3f93ab 100644
--- a/python/m5/config.py
+++ b/python/m5/config.py
@@ -1096,12 +1096,20 @@ def tick_check(float_ticks):
     err = (float_ticks - int_ticks) / float_ticks
     if err > frequency_tolerance:
         print >> sys.stderr, "Warning: rounding error > tolerance"
+        print >> sys.stderr, "    %f rounded to %d" % (float_ticks, int_ticks)
+        #raise ValueError
     return int_ticks
 
 # superclass for "numeric" parameter values, to emulate math
 # operations in a type-safe way.  e.g., a Latency times an int returns
 # a new Latency object.
 class NumericParamValue(ParamValue):
+    def __str__(self):
+        return str(self.value)
+
+    def __float__(self):
+        return float(self.value)
+
     def __mul__(self, other):
         newobj = self.__class__(self)
         newobj.value *= other
@@ -1109,27 +1117,31 @@ class NumericParamValue(ParamValue):
 
     __rmul__ = __mul__
 
-class Latency(NumericParamValue):
-    def __init__(self, value):
-        if isinstance(value, Latency):
-            self.value = value.value
-        elif isinstance(value, Frequency):
-            self.value = 1 / value.value
-        elif isinstance(value, str):
+    def __div__(self, other):
+        newobj = self.__class__(self)
+        newobj.value /= other
+        return newobj
+
+
+def getLatency(value):
+    if isinstance(value, Latency) or isinstance(value, Clock):
+        return value.value
+    elif isinstance(value, Frequency) or isinstance(value, RootClock):
+        return 1 / value.value
+    elif isinstance(value, str):
+        try:
+            return toLatency(value)
+        except ValueError:
             try:
-                self.value = toLatency(value)
+                return 1 / toFrequency(value)
             except ValueError:
-                try:
-                    freq = toFrequency(value)
-                except ValueError:
-                    raise ValueError, "Latency value '%s' is neither " \
-                          "frequency nor period" % value
-                self.value = 1 / freq
-        elif value == 0:
-            # the one unitless value that's OK...
-            self.value = value
-        else:
-            raise ValueError, "Invalid Latency value '%s'" % value
+                pass # fall through
+    raise ValueError, "Invalid Frequency/Latency value '%s'" % value
+
+
+class Latency(NumericParamValue):
+    def __init__(self, value):
+        self.value = getLatency(value)
 
     def __getattr__(self, attr):
         if attr in ('latency', 'period'):
@@ -1138,31 +1150,13 @@ class Latency(NumericParamValue):
             return Frequency(self)
         raise AttributeError, "Latency object has no attribute '%s'" % attr
 
-    def __str__(self):
-        return str(self.value)
-
     # convert latency to ticks
     def ini_str(self):
         return str(tick_check(self.value * ticks_per_sec))
 
 class Frequency(NumericParamValue):
     def __init__(self, value):
-        if isinstance(value, Frequency):
-            self.value = value.value
-        elif isinstance(value, Latency):
-            self.value = 1 / value.value
-        elif isinstance(value, str):
-            try:
-                self.value = toFrequency(value)
-            except ValueError:
-                try:
-                    freq = toLatency(value)
-                except ValueError:
-                    raise ValueError, "Frequency value '%s' is neither " \
-                          "frequency nor period" % value
-                self.value = 1 / freq
-        else:
-            raise ValueError, "Invalid Frequency value '%s'" % value
+        self.value = 1 / getLatency(value)
 
     def __getattr__(self, attr):
         if attr == 'frequency':
@@ -1171,21 +1165,44 @@ class Frequency(NumericParamValue):
             return Latency(self)
         raise AttributeError, "Frequency object has no attribute '%s'" % attr
 
-    def __str__(self):
-        return str(self.value)
-
-    def __float__(self):
-        return float(self.value)
-
     # convert frequency to ticks per period
     def ini_str(self):
         return self.period.ini_str()
 
-# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz)
-class RootFrequency(Frequency):
+# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz).
+# We can't inherit from Frequency because we don't want it to be directly
+# assignable to a regular Frequency parameter.
+class RootClock(ParamValue):
+    def __init__(self, value):
+        self.value = 1 / getLatency(value)
+
+    def __getattr__(self, attr):
+        if attr == 'frequency':
+            return Frequency(self)
+        if attr in ('latency', 'period'):
+            return Latency(self)
+        raise AttributeError, "Frequency object has no attribute '%s'" % attr
+
     def ini_str(self):
         return str(tick_check(self.value))
 
+# A generic frequency and/or Latency value.  Value is stored as a latency,
+# but to avoid ambiguity this object does not support numeric ops (* or /).
+# An explicit conversion to a Latency or Frequency must be made first.
+class Clock(ParamValue):
+    def __init__(self, value):
+        self.value = getLatency(value)
+
+    def __getattr__(self, attr):
+        if attr == 'frequency':
+            return Frequency(self)
+        if attr in ('latency', 'period'):
+            return Latency(self)
+        raise AttributeError, "Frequency object has no attribute '%s'" % attr
+
+    def ini_str(self):
+        return self.period.ini_str()
+
 class NetworkBandwidth(float,ParamValue):
     def __new__(cls, value):
         val = toNetworkBandwidth(value) / 8.0
@@ -1223,7 +1240,7 @@ AllMemory = AddrRange(0, MaxAddr)
 # script once config is built.
 def instantiate(root):
     global ticks_per_sec
-    ticks_per_sec = float(root.frequency)
+    ticks_per_sec = float(root.clock.frequency)
     root.print_ini()
     noDot = True # temporary until we fix dot
     if not noDot:
@@ -1246,7 +1263,7 @@ __all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam',
            'Int32', 'UInt32', 'Int64', 'UInt64',
            'Counter', 'Addr', 'Tick', 'Percent',
            'TcpPort', 'UdpPort', 'EthernetAddr',
-           'MemorySize', 'Latency', 'Frequency', 'RootFrequency',
+           'MemorySize', 'Latency', 'Frequency', 'RootClock', 'Clock',
            'NetworkBandwidth', 'MemoryBandwidth',
            'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory',
            'Null', 'NULL',
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index d4fa13d3b..0dc436434 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -25,4 +25,4 @@ class BaseCPU(SimObject):
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
+    clock = Param.Clock(Parent.clock, "clock speed")
diff --git a/python/m5/objects/BaseCache.py b/python/m5/objects/BaseCache.py
index d311969fa..79d21572a 100644
--- a/python/m5/objects/BaseCache.py
+++ b/python/m5/objects/BaseCache.py
@@ -11,7 +11,7 @@ class BaseCache(BaseMem):
     block_size = Param.Int("block size in bytes")
     compressed_bus = Param.Bool(False,
         "This cache connects to a compressed memory")
-    compression_latency = Param.Latency(0,
+    compression_latency = Param.Latency('0ns',
         "Latency in cycles of compression algorithm")
     do_copy = Param.Bool(False, "perform fast copies in the cache")
     hash_delay = Param.Int(1, "time in cycles of hash access")
diff --git a/python/m5/objects/BaseSystem.py b/python/m5/objects/BaseSystem.py
index 48c70e44f..457eadb36 100644
--- a/python/m5/objects/BaseSystem.py
+++ b/python/m5/objects/BaseSystem.py
@@ -2,7 +2,7 @@ from m5 import *
 class BaseSystem(SimObject):
     type = 'BaseSystem'
     abstract = True
-    boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency,
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                          "boot processor frequency")
     memctrl = Param.MemoryController(Parent.any, "memory controller")
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py
index 1ed87d2e7..26509d7d2 100644
--- a/python/m5/objects/Bus.py
+++ b/python/m5/objects/Bus.py
@@ -3,5 +3,5 @@ from BaseHier import BaseHier
 
 class Bus(BaseHier):
     type = 'Bus'
-    clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
+    clock = Param.Clock("bus frequency")
     width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 69dec1528..c89505477 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -58,7 +58,7 @@ class NSGigE(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+    clock = Param.Clock('100MHz', "State machine processor frequency")
 
     dma_data_free = Param.Bool(False, "DMA of Data is free")
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@@ -95,7 +95,7 @@ class Sinic(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+    clock = Param.Clock('100MHz', "State machine processor frequency")
 
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
index 78d5388f0..79e3721fc 100644
--- a/python/m5/objects/Root.py
+++ b/python/m5/objects/Root.py
@@ -6,7 +6,7 @@ from Trace import Trace
 
 class Root(SimObject):
     type = 'Root'
-    frequency = Param.RootFrequency('200MHz', "tick frequency")
+    clock = Param.RootClock('200MHz', "tick frequency")
     output_file = Param.String('cout', "file to dump simulator output to")
     checkpoint = Param.String('', "checkpoint file to load")
 #    hier = Param.HierParams(HierParams(do_data = False, do_events = True),