summaryrefslogtreecommitdiff
path: root/python/m5
diff options
context:
space:
mode:
authorNathan Binkert <binkertn@umich.edu>2005-11-21 00:02:39 -0500
committerNathan Binkert <binkertn@umich.edu>2005-11-21 00:02:39 -0500
commitc4678ece8414230005e7a9e41e50e48c1bba66d7 (patch)
tree10e1cab63ea34bf56cd8bfde4f3856ec8b4d26cd /python/m5
parentd733d168ca104ce690ca5f3396d7b3e336f16db2 (diff)
downloadgem5-c4678ece8414230005e7a9e41e50e48c1bba66d7.tar.xz
BARs now of type MemorySize32
python/m5/config.py: Add MemorySize32 (a 32-bit value specified in bytes) --HG-- extra : convert_revision : bfeee501f7ff1aa2567a3682da129a5770cb7bd2
Diffstat (limited to 'python/m5')
-rw-r--r--python/m5/config.py12
-rw-r--r--python/m5/objects/Pci.py12
2 files changed, 17 insertions, 7 deletions
diff --git a/python/m5/config.py b/python/m5/config.py
index 23292d2dc..a954012ea 100644
--- a/python/m5/config.py
+++ b/python/m5/config.py
@@ -972,6 +972,15 @@ class MemorySize(CheckedInt):
self.value = toMemorySize(value)
self._check()
+class MemorySize32(CheckedInt):
+ size = 32
+ unsigned = True
+ def __init__(self, value):
+ if isinstance(value, MemorySize):
+ self.value = value.value
+ else:
+ self.value = toMemorySize(value)
+ self._check()
class Addr(CheckedInt):
size = 64
@@ -1305,7 +1314,8 @@ __all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam',
'Int32', 'UInt32', 'Int64', 'UInt64',
'Counter', 'Addr', 'Tick', 'Percent',
'TcpPort', 'UdpPort', 'EthernetAddr',
- 'MemorySize', 'Latency', 'Frequency', 'RootClock', 'Clock',
+ 'MemorySize', 'MemorySize32',
+ 'Latency', 'Frequency', 'RootClock', 'Clock',
'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory',
'Null', 'NULL',
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
index defdd10a3..4124d0b92 100644
--- a/python/m5/objects/Pci.py
+++ b/python/m5/objects/Pci.py
@@ -22,12 +22,12 @@ class PciConfigData(SimObject):
BAR3 = Param.UInt32(0x00, "Base Address Register 3")
BAR4 = Param.UInt32(0x00, "Base Address Register 4")
BAR5 = Param.UInt32(0x00, "Base Address Register 5")
- BAR0Size = Param.UInt32(0, "Base Address Register 0 Size")
- BAR1Size = Param.UInt32(0, "Base Address Register 1 Size")
- BAR2Size = Param.UInt32(0, "Base Address Register 2 Size")
- BAR3Size = Param.UInt32(0, "Base Address Register 3 Size")
- BAR4Size = Param.UInt32(0, "Base Address Register 4 Size")
- BAR5Size = Param.UInt32(0, "Base Address Register 5 Size")
+ BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
+ BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
+ BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
+ BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
+ BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
+ BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
SubsystemID = Param.UInt16(0x00, "Subsystem ID")