diff options
| author | Nathan Binkert <binkertn@umich.edu> | 2005-05-02 19:00:11 -0400 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2005-05-02 19:00:11 -0400 |
| commit | 364f6e32354b1e8188660d398ea2c7cb5b222fc9 (patch) | |
| tree | 41621f0a23ece44194155e8d69e22b3260820e80 /python/m5 | |
| parent | 5921d6beb8684044a85ba1f7af296cd7b036c7ea (diff) | |
| download | gem5-364f6e32354b1e8188660d398ea2c7cb5b222fc9.tar.xz | |
Make sinic work with mpy
dev/sinic.cc:
dev/sinic.hh:
Fix sinic parameters. (header_bus -> io_bus)
python/m5/objects/Ethernet.mpy:
Add simobj definitions for sinic.
--HG--
extra : convert_revision : 77d5b80bd1f1708329b263fb48965d7f555cc9d1
Diffstat (limited to 'python/m5')
| -rw-r--r-- | python/m5/objects/Ethernet.mpy | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy index 141d138da..0065a238f 100644 --- a/python/m5/objects/Ethernet.mpy +++ b/python/m5/objects/Ethernet.mpy @@ -89,4 +89,33 @@ simobj NSGigEInt(EtherInt): type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") +simobj Sinic(PciDevice): + type = 'Sinic' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + + rx_max_copy = Param.MemorySize('16kB', "rx max copy") + tx_max_copy = Param.MemorySize('16kB', "tx max copy") + rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo") + tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo") + rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold") + tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold") + + intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(parent.any, "Physical Memory") +simobj SinicInt(EtherInt): + type = 'SinicInt' + device = Param.Sinic("Ethernet device of this interface") |