Hand merge. Stuff probably doesn't compile.

--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8

2 files changed, 17 insertions, 15 deletions

diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 2edc7576e..22714e15c 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -75,7 +75,6 @@ class EtherDevBase(PciDevice):
     dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
     dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
     dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-    pio_delay_write = Param.Bool(False, "Delay pio writes until timing occurs")
 
     rx_delay = Param.Latency('1us', "Receive Delay")
     tx_delay = Param.Latency('1us', "Transmit Delay")
@@ -86,6 +85,7 @@ class EtherDevBase(PciDevice):
     intr_delay = Param.Latency('10us', "Interrupt propagation delay")
     rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
     tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
+    rss = Param.Bool(False, "Receive Side Scaling")
 
 class NSGigE(EtherDevBase):
     type = 'NSGigE'
diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py
index 8c5d93f7b..5925cadf5 100644
--- a/python/m5/objects/System.py
+++ b/python/m5/objects/System.py
@@ -1,19 +1,21 @@
 from m5 import *
+
 class System(SimObject):
     type = 'System'
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+                                         "boot processor frequency")
+    memctrl = Param.MemoryController(Parent.any, "memory controller")
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
+    init_param = Param.UInt64(0, "numerical value to pass into simulator")
+    bin = Param.Bool(False, "is this system binned")
+    binned_fns = VectorParam.String([], "functions broken down and binned")
+    kernel = Param.String("file that contains the kernel code")
+    readfile = Param.String("", "file to read startup script from")
 
-    if build_env['FULL_SYSTEM']:
-        boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
-                                             "boot processor frequency")
-        memctrl = Param.MemoryController(Parent.any, "memory controller")
-        kernel = Param.String("file that contains the kernel code")
-        console = Param.String("file that contains the console code")
-        pal = Param.String("file that contains palcode")
-        readfile = Param.String("", "file to read startup script from")
-        init_param = Param.UInt64(0, "numerical value to pass into simulator")
-        boot_osflags = Param.String("a", "boot flags to pass to the kernel")
-        system_type = Param.UInt64("Type of system we are emulating")
-        system_rev = Param.UInt64("Revision of system we are emulating")
-        bin = Param.Bool(False, "is this system binned")
-        binned_fns = VectorParam.String([], "functions broken down and binned")
+class AlphaSystem(System):
+    type = 'AlphaSystem'
+    console = Param.String("file that contains the console code")
+    pal = Param.String("file that contains palcode")
+    boot_osflags = Param.String("a", "boot flags to pass to the kernel")
+    system_type = Param.UInt64("Type of system we are emulating")
+    system_rev = Param.UInt64("Revision of system we are emulating")