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author | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-26 21:44:22 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-26 21:44:22 -0500 |
commit | c27c122afc6b778e67a9c77915fac71730a5a4ef (patch) | |
tree | 3056d2ebc1c9eb74fc8d850a942666ce46ad2026 /python | |
parent | 4973a16b34471dcb5f65a1d6c31d5a7d8c2dfd83 (diff) | |
download | gem5-c27c122afc6b778e67a9c77915fac71730a5a4ef.tar.xz |
Add the bus and connector objects to scons
change getPort parameter from char* to string
Add an extra phase between construction and init called connect
SConscript:
Add the bus and connector objects to scons
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
the connection to memory shouldn't be made until we know the memory
object exists (e.g. after construction)
dev/io_device.hh:
change to const string
mem/bus.hh:
change getPort parameter from char* to string
initialize num_interfaces
mem/mem_object.hh:
change getPort parameter from char* to string
mem/physical.cc:
mem/physical.hh:
change getPort parameter from char* to string
get rid of the bus object I created last time
python/m5/objects/PhysicalMemory.py:
get rid of the bus object I created last time
sim/main.cc:
sim/sim_object.cc:
sim/sim_object.hh:
Add an extra phase between construction and init called connect
--HG--
extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
Diffstat (limited to 'python')
-rw-r--r-- | python/m5/objects/PhysicalMemory.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py index 7c5a0c517..b0aba1a7d 100644 --- a/python/m5/objects/PhysicalMemory.py +++ b/python/m5/objects/PhysicalMemory.py @@ -5,6 +5,5 @@ class PhysicalMemory(Memory): type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") - bus = Param.MemObject("Bus to attach to") if build_env['FULL_SYSTEM']: mmu = Param.MemoryController(Parent.any, "Memory Controller") |