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author | Nathan Binkert <binkertn@umich.edu> | 2005-11-25 13:33:36 -0500 |
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committer | Nathan Binkert <binkertn@umich.edu> | 2005-11-25 13:33:36 -0500 |
commit | 47ff0af17e4494ed99c6eebbf8c6b742f7f7dacf (patch) | |
tree | 227376761e1ebee0aba84920e45bb36ab2bec6c6 /python | |
parent | 60e92986f739a025a6534972b8e1cf9498ce3fd2 (diff) | |
download | gem5-47ff0af17e4494ed99c6eebbf8c6b742f7f7dacf.tar.xz |
Virtualize sinic
separate the rx thread and tx thread and get rid of the dedicated flag.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
python/m5/objects/Ethernet.py:
dedicated flag goes away, we have new individual flags for
rx thread and tx thread
dev/sinic.cc:
Virtualize sinic
- The io registers are replicated many times in memory, allowing the NIC to
differentiate among several virtual interfaces.
- On the TX side, this allows multiple CPUs to initiate transmits at the same
time without locking in the software. If a partial packet is transmitted,
then the state machine blocks waiting for that virtual interface to complete
its packet. Then the state machine will move on to the next virtual
interface. The commands are kept in fifo order.
- On the RX side, multiple partial transmits can be simultaneously done.
Though a packet does not deallocate its fifo space until all preceeding
packets in the fifo are deallocated. To enable multiple receives, it
is necessary for each virtual nic to keep its own information about its
progress through the state machine.
dev/sinic.hh:
Virtualize sinic
Receive state must be virtualized since we allow the receipt of packets in
parallel.
dev/sinicreg.hh:
Virtualize sinic
separate rx thread and tx thread
create a soft interrupt and add a command to trigger it.
pad out the reserved bits in the RxDone and TxDone regs
--HG--
extra : convert_revision : c10bb23a46a89ffd1e08866c1f1621cb98069205
Diffstat (limited to 'python')
-rw-r--r-- | python/m5/objects/Ethernet.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 491ca4d9f..f58ece0be 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -84,8 +84,9 @@ class EtherDevBase(PciDevice): tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") rx_filter = Param.Bool(True, "Enable Receive Filter") - intr_delay = Param.Latency('10us', "Interrupt Propagation Delay") - dedicated = Param.Bool(False, "dedicate a kernel thread to the driver") + intr_delay = Param.Latency('10us', "Interrupt propagation delay") + rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") + tx_thread = Param.Bool(False, "dedicated kernel threads for receive") class NSGigE(EtherDevBase): type = 'NSGigE' |