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author | Kevin Lim <ktlim@umich.edu> | 2005-05-04 14:41:36 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2005-05-04 14:41:36 -0400 |
commit | c03e97b62d2adbe335a883b5fafa10c973e2c4d1 (patch) | |
tree | 8693177258ba24ac957e35ba1a0da97fcbef254b /python | |
parent | 61d95de4c886911fa0b7dc9d587ffe5b292b739e (diff) | |
parent | 3b0464127e3512ac0865fa8e6207085d49692ae8 (diff) | |
download | gem5-c03e97b62d2adbe335a883b5fafa10c973e2c4d1.tar.xz |
Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
--HG--
extra : convert_revision : b868e7920eaa3682c6123651f0c598673ebb7f22
Diffstat (limited to 'python')
-rw-r--r-- | python/m5/objects/Ethernet.mpy | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy index 141d138da..0065a238f 100644 --- a/python/m5/objects/Ethernet.mpy +++ b/python/m5/objects/Ethernet.mpy @@ -89,4 +89,33 @@ simobj NSGigEInt(EtherInt): type = 'NSGigEInt' device = Param.NSGigE("Ethernet device of this interface") +simobj Sinic(PciDevice): + type = 'Sinic' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + cycle_time = Param.Frequency('100MHz', "State machine processor frequency") + + dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") + dma_read_factor = Param.Latency('0us', "multiplier for dma reads") + dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") + dma_write_factor = Param.Latency('0us', "multiplier for dma writes") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Latency('1us', "Receive Delay") + tx_delay = Param.Latency('1us', "Transmit Delay") + + rx_max_copy = Param.MemorySize('16kB', "rx max copy") + tx_max_copy = Param.MemorySize('16kB', "tx max copy") + rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo") + tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo") + rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold") + tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold") + + intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(parent.any, "Physical Memory") +simobj SinicInt(EtherInt): + type = 'SinicInt' + device = Param.Sinic("Ethernet device of this interface") |