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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-01 19:39:23 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-04-01 19:39:23 -0500 |
| commit | fdceb0f00c518652c34530d46e877354db78e4aa (patch) | |
| tree | 0e24be9a7c5b4108714649c1088674fdbcafc5d0 /python | |
| parent | 9ba57eafc27cab28e8a172539e013d2f762a1dd0 (diff) | |
| parent | c21bf8e7aebe9157488f300edbf378d9a2d3cf71 (diff) | |
| download | gem5-fdceb0f00c518652c34530d46e877354db78e4aa.tar.xz | |
Some hand merges
--HG--
rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy
extra : convert_revision : b24ff4c1feb480cf280207d4bbdfe08ef80d1aa2
Diffstat (limited to 'python')
| -rw-r--r-- | python/m5/objects/BaseCache.mpy | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index b9986917f..198665325 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -36,3 +36,12 @@ simobj BaseCache(BaseMem): two_queue = Param.Bool(False, "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") + prefetch_miss = Param.Bool(False, + "wheter you are using the hardware prefetcher from Miss stream") + prefetch_access = Param.Bool(False, + "wheter you are using the hardware prefetcher from Access stream") + prefetcher_size = Param.Int(100, + "Number of entries in the harware prefetch queue") + prefetch_past_page = Param.Bool(False, + "Allow prefetches to cross virtual page boundaries") + |