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authorKevin Lim <ktlim@umich.edu>2006-05-16 14:47:09 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-16 14:47:09 -0400
commitabe14c253b64eb3c991309bf24db60103095c70d (patch)
tree1f637b943ea4fb4d19a1b3fb6ee186e3fa5de1e7 /python
parent52383ca7cc2b4698109b71a968cde16e9f7dc6e0 (diff)
downloadgem5-abe14c253b64eb3c991309bf24db60103095c70d.tar.xz
Include checker and trap latency parameters.
--HG-- extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42
Diffstat (limited to 'python')
-rw-r--r--python/m5/objects/AlphaFullCPU.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py
index 284398b0e..1541b9494 100644
--- a/python/m5/objects/AlphaFullCPU.py
+++ b/python/m5/objects/AlphaFullCPU.py
@@ -9,6 +9,8 @@ class DerivAlphaFullCPU(BaseCPU):
if not build_env['FULL_SYSTEM']:
mem = Param.FunctionalMemory(NULL, "memory")
+ checker = Param.BaseCPU(NULL, "checker")
+
cachePorts = Param.Unsigned("Cache Ports")
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
@@ -50,6 +52,8 @@ class DerivAlphaFullCPU(BaseCPU):
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
commitWidth = Param.Unsigned("Commit width")
squashWidth = Param.Unsigned("Squash width")
+ trapLatency = Param.Tick("Trap latency")
+ fetchTrapLatency = Param.Tick("Fetch trap latency")
localPredictorSize = Param.Unsigned("Size of local predictor")
localCtrBits = Param.Unsigned("Bits per counter")