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authorNathan Binkert <binkertn@umich.edu>2005-11-21 23:43:15 -0500
committerNathan Binkert <binkertn@umich.edu>2005-11-21 23:43:15 -0500
commitf806a25c9edb3a9a9f5bc34b88340be6b24a2022 (patch)
tree054c4562aabde4aaf354f764dd88b029dbe3f858 /python
parent50ee8c646128a9e08051843535076f12f6c6dfea (diff)
downloadgem5-f806a25c9edb3a9a9f5bc34b88340be6b24a2022.tar.xz
add support for delaying pio writes until the cache access occurs
dev/ns_gige.cc: add support for delaying pio writes until the cache access occurs the only write we delay are for CR_TXE and CR_RXE dev/sinic.cc: dev/sinic.hh: the txPioRequest and rxPioRequest things were more or less bogus add support for delaying pio writes until the cache access occurs dev/sinicreg.hh: Add delay_read and delay_write to the register information struct for now, we won't delay any reads, and we'll delay the writes that initiate DMAs python/m5/objects/Ethernet.py: add a parameter to delay pio writes until the timing access actually occurs. --HG-- extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d
Diffstat (limited to 'python')
-rw-r--r--python/m5/objects/Ethernet.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index a2a8b217f..491ca4d9f 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -76,6 +76,7 @@ class EtherDevBase(PciDevice):
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+ pio_delay_write = Param.Bool(False, "Delay pio writes until timing occurs")
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")