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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-02-21 16:50:38 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-02-21 16:50:38 -0500 |
| commit | 9dd1ab1dba6f72f11ce4985a166cb1327eee3551 (patch) | |
| tree | a9eed695686a885021901129a5fb91d02ca05b60 /sim/main.cc | |
| parent | f825d103daa2eeaa26549862cd57d870aa1cb448 (diff) | |
| parent | 9b1e2db811f86d9911bacaad475d1fec70c4aecd (diff) | |
| download | gem5-9dd1ab1dba6f72f11ce4985a166cb1327eee3551.tar.xz | |
Merge zizzer:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1
--HG--
extra : convert_revision : db688679bfd9c670ef44611de71640c3bf564fc0
Diffstat (limited to 'sim/main.cc')
| -rw-r--r-- | sim/main.cc | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/sim/main.cc b/sim/main.cc index 4352a90f4..c15d24453 100644 --- a/sim/main.cc +++ b/sim/main.cc @@ -402,12 +402,6 @@ main(int argc, char **argv) // Reset to put the stats in a consistent state. Stats::reset(); - // Nothing to simulate if we don't have at least one CPU somewhere. - if (BaseCPU::numSimulatedCPUs() == 0) { - cerr << "Fatal: no CPUs to simulate." << endl; - exit(1); - } - warn("Entering event queue. Starting simulation...\n"); SimStartup(); while (!mainEventQueue.empty()) { |