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authorSteve Reinhardt <stever@eecs.umich.edu>2003-12-11 00:16:46 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2003-12-11 00:16:46 -0800
commit777c1ebfab0318d4b98834b0f2ef48a2de16b8dd (patch)
tree448b7f195d862ca9398e296d1b18e1cae33f49d5 /sim/main.cc
parent7e6dcd812c18060a76d5a73a97e4aa05bcb0d516 (diff)
downloadgem5-777c1ebfab0318d4b98834b0f2ef48a2de16b8dd.tar.xz
Stats & serialization tweaks & cleanup. Unserializing from
a checkpoint now gives identical results to running from scratch and doing at switchover at the same cycle! - CPUs start at cycle 0 again, not cycle 1. - curTick is now serialized & unserialized. - Stats get reset in main (before event loop). Since this is done after curTick is unserialized, simTicks gets set correctly for running from a checkpoint. - Simplify serialization to happen in a single pass. - s/Serializeable/Serializable/ arch/alpha/isa_traits.hh: dev/etherlink.hh: sim/eventq.cc: sim/eventq.hh: s/Serializeable/Serializable/ kern/tru64/tru64_system.cc: sim/process.cc: Make initial CPU activation on cycle 0 again (not 1). sim/main.cc: Reset stats before getting started. Make error message on falling out of event loop more meaningful. sim/serialize.cc: sim/serialize.hh: Get rid of now-useless initial pass; serialization is done in a single pass now. Serialize & unserialize curTick. Wrap curTick and mainEventQueue in a "globals" Serializable object. s/Serializeable/Serializable/ sim/sim_object.cc: Add static function to serialize all SimObjects. sim/sim_object.hh: Add static function to serialize all SimObjects. s/Serializeable/Serializable/ --HG-- extra : convert_revision : 9dcc411d0009b54b8eb61c3a509680b81b9f6f68
Diffstat (limited to 'sim/main.cc')
-rw-r--r--sim/main.cc5
1 files changed, 4 insertions, 1 deletions
diff --git a/sim/main.cc b/sim/main.cc
index f697aebce..287b3d6e6 100644
--- a/sim/main.cc
+++ b/sim/main.cc
@@ -389,6 +389,9 @@ main(int argc, char **argv)
// Check to make sure that the stats package is properly initialized
Statistics::check();
+ // Reset to put the stats in a consistent state.
+ Statistics::reset();
+
// Nothing to simulate if we don't have at least one CPU somewhere.
if (BaseCPU::numSimulatedCPUs() == 0) {
cerr << "Fatal: no CPUs to simulate." << endl;
@@ -437,7 +440,7 @@ main(int argc, char **argv)
// simulation to terminate (hit max cycles/insts, signal,
// simulated system halts/exits) generates an exit event, so we
// should never run out of events on the queue.
- exitNow("improperly exited event loop!", 1);
+ exitNow("no events on event loop! All CPUs must be idle.", 1);
return 0;
}