Replace Memory with MemObject; no need for two different levels of hierarchy there.

Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f

1 files changed, 18 insertions, 3 deletions

diff --git a/sim/process.cc b/sim/process.cc
index 2eeb87234..80f787062 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -39,7 +39,7 @@
 #include "config/full_system.hh"
 #include "cpu/exec_context.hh"
 #include "mem/page_table.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
 #include "mem/translating_port.hh"
 #include "sim/builder.hh"
 #include "sim/process.hh"
@@ -149,13 +149,27 @@ Process::startup()
     if (execContexts.empty())
         fatal("Process %s is not associated with any CPUs!\n", name());
 
-    initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
-
     // first exec context for this process... initialize & enable
     ExecContext *xc = execContexts[0];
 
     // mark this context as active so it will start ticking.
     xc->activate(0);
+
+    // Here we are grabbing the memory port of the CPU hosting the
+    // initial execution context for initialization.  In the long run
+    // this is not what we want, since it means that all
+    // initialization accesses (e.g., loading object file sections)
+    // will be done a cache block at a time through the CPU's cache.
+    // We really want something more like:
+    //
+    // memport = system->physmem->getPort();
+    // myPort.setPeer(memport);
+    // memport->setPeer(&myPort);
+    // initVirtMem = new TranslatingPort(myPort, pTable);
+    //
+    // but we need our own dummy port "myPort" that doesn't exist.
+    // In the short term it works just fine though.
+    initVirtMem = xc->getMemPort();
 }
 
 void
@@ -367,6 +381,7 @@ LiveProcess::syscall(ExecContext *xc)
     desc->doSyscall(callnum, this, xc);
 }
 
+
 LiveProcess *
 LiveProcess::create(const string &nm, System *system,
                     int stdin_fd, int stdout_fd, int stderr_fd,