diff options
author | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-20 23:56:10 -0500 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-20 23:56:10 -0500 |
commit | 33913542859fa2bef15765009ae33d5e724bb0b0 (patch) | |
tree | 0a21e20c5e18eb64ff74e2abff61298d3379653e /sim/process.hh | |
parent | d96de69abc02b40e1dec4843a7a7b7e30749f4fa (diff) | |
download | gem5-33913542859fa2bef15765009ae33d5e724bb0b0.tar.xz |
Make loaders use translation port instead of proxy memory.
Also start compiling Simple CPU again.
SConscript:
Start Compiling Simple CPU as well
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
sim/process.cc:
sim/process.hh:
Convert loaders to used translation port instead of proxy memory
--HG--
extra : convert_revision : 63275071f6a0e0d71935641205b203d94381ee44
Diffstat (limited to 'sim/process.hh')
-rw-r--r-- | sim/process.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/process.hh b/sim/process.hh index cdd28982d..8d8c9e676 100644 --- a/sim/process.hh +++ b/sim/process.hh @@ -50,7 +50,7 @@ #include "targetarch/isa_traits.hh" class ExecContext; -class Memory; +class TranslatingPort; class System; class Process : public SimObject @@ -128,7 +128,7 @@ class Process : public SimObject protected: /// Memory object for initialization (image loading) - Memory *initVirtMem; + TranslatingPort *initVirtMem; public: PageTable *pTable; |