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author | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-09 00:17:09 -0500 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2005-03-09 00:17:09 -0500 |
commit | 4b69debac6ce72fe46a8d8b5284c740e338f06f6 (patch) | |
tree | fa91d247f571c4bf6645ca808f9ea04309643891 /sim/pyconfig | |
parent | e5f945967b2d49f3c14384be947a12dbf02260da (diff) | |
download | gem5-4b69debac6ce72fe46a8d8b5284c740e338f06f6.tar.xz |
Fix a couple of bugs introduced (or tickled) by the .ini sorting change.
sim/pyconfig/m5config.py:
Don't sort child nodes, as this can change timing in memory system.
(Really ought to be fixed in memory system, but we'll just take the
sort back out for now to avoid intoducing gratuitous changes.)
--HG--
extra : convert_revision : 07e950c25911443cbc7a84435969ca596fb04348
Diffstat (limited to 'sim/pyconfig')
-rw-r--r-- | sim/pyconfig/m5config.py | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py index 17a0d8f42..330d7e878 100644 --- a/sim/pyconfig/m5config.py +++ b/sim/pyconfig/m5config.py @@ -697,8 +697,12 @@ class Node(object): if self.children: # instantiate children in same order they were added for # backward compatibility (else we can end up with cpu1 - # before cpu0). - self.children.sort(lambda x,y: cmp(x.name, y.name)) + # before cpu0). Changing ordering can also influence timing + # in the current memory system, as caches get added to a bus + # in different orders which affects their priority in the + # case of simulataneous requests. We should uncomment the + # following line once we take care of that issue. + # self.children.sort(lambda x,y: cmp(x.name, y.name)) children = [ c.name for c in self.children if not c.paramcontext] print 'children =', ' '.join(children) |