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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-05-09 20:14:18 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-05-09 20:14:18 -0400 |
| commit | 3c7071a6be21fc0c87753758fc09ff28890edc99 (patch) | |
| tree | a19a9f044f9016f0f9a45875d3fde685d79de6a0 /sim/sim_object.cc | |
| parent | 4a5dcc37bfb26c152c195061fa70c7aa246b5ca6 (diff) | |
| download | gem5-3c7071a6be21fc0c87753758fc09ff28890edc99.tar.xz | |
Added ULL for 64bit ints
Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.
arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
Added ULL for 64bit ints
kern/linux/linux_system.cc:
Added a function to skip determine_cpu_caches, right now it is only used for
printing in proc, however in the future we may either want to implement the SC_CTL
IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
added event to skip determine_cpu_caches()
--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
Diffstat (limited to 'sim/sim_object.cc')
0 files changed, 0 insertions, 0 deletions