Add support for multiple ports on the memory. Hook up simple cpu to memory.

Ready to start testing if I could fix the linking errors I can't ever seem to fix.

cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Add connecting of ports until builder can handle it.
mem/physical.cc:
    Add function to allocate a port in the object

    Remove some full_sys stuff untill needed
mem/physical.hh:
    Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
    Update the params
sim/process.cc:
    Make sure to use the right name (hopefully CPU constructor already called)

--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85

1 files changed, 1 insertions, 1 deletions

diff --git a/sim/process.cc b/sim/process.cc
index 2335d5cc8..ac2aae5d4 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -154,7 +154,7 @@ Process::startup()
     if (execContexts.empty())
         fatal("Process %s is not associated with any CPUs!\n", name());
 
-    initVirtMem = new TranslatingPort((system->physmem->getPort("any"))->getPeer(), pTable);
+    initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
 
     // first exec context for this process... initialize & enable
     ExecContext *xc = execContexts[0];