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authorSteve Reinhardt <stever@eecs.umich.edu>2006-03-12 17:21:59 -0500
committerSteve Reinhardt <stever@eecs.umich.edu>2006-03-12 17:21:59 -0500
commite2b329d574483096da64d4050a9a0b228757a72e (patch)
tree1eaa5625be7cc5132c91a948771479141878a564 /sim
parent2d9c9dba37499d87ee599388aca5502279ce953a (diff)
downloadgem5-e2b329d574483096da64d4050a9a0b228757a72e.tar.xz
Replace Memory with MemObject; no need for two different levels of hierarchy there.
Get rid of addPort(). Change getPort() behavior on PhysicalMemory. SConscript: cpu/simple/cpu.hh: sim/system.cc: sim/system.hh: Replace Memory with MemObject. cpu/base.hh: No need to declare Port here anymore. cpu/cpu_exec_context.hh: Need PageTable definition. cpu/simple/cpu.cc: mem/physical.cc: mem/physical.hh: Replace Memory with MemObject. Get rid of addPort(); allow getting anonymous ports with getPort(). mem/translating_port.hh: Remove unneeded header. sim/process.cc: Replace Memory with MemObject. Change how initialization port gets set up to deal with change in addPort()/getPort(). Current solution is not ideal but it works. sim/process.hh: Remove unneeded headers and declarations. Make LiveProcess::getDesc() abstract instead of panicing if called. sim/syscall_emul.hh: Fix includes. --HG-- extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
Diffstat (limited to 'sim')
-rw-r--r--sim/process.cc21
-rw-r--r--sim/process.hh14
-rw-r--r--sim/syscall_emul.hh2
-rw-r--r--sim/system.cc4
-rw-r--r--sim/system.hh6
5 files changed, 26 insertions, 21 deletions
diff --git a/sim/process.cc b/sim/process.cc
index 2eeb87234..80f787062 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -39,7 +39,7 @@
#include "config/full_system.hh"
#include "cpu/exec_context.hh"
#include "mem/page_table.hh"
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
#include "mem/translating_port.hh"
#include "sim/builder.hh"
#include "sim/process.hh"
@@ -149,13 +149,27 @@ Process::startup()
if (execContexts.empty())
fatal("Process %s is not associated with any CPUs!\n", name());
- initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
-
// first exec context for this process... initialize & enable
ExecContext *xc = execContexts[0];
// mark this context as active so it will start ticking.
xc->activate(0);
+
+ // Here we are grabbing the memory port of the CPU hosting the
+ // initial execution context for initialization. In the long run
+ // this is not what we want, since it means that all
+ // initialization accesses (e.g., loading object file sections)
+ // will be done a cache block at a time through the CPU's cache.
+ // We really want something more like:
+ //
+ // memport = system->physmem->getPort();
+ // myPort.setPeer(memport);
+ // memport->setPeer(&myPort);
+ // initVirtMem = new TranslatingPort(myPort, pTable);
+ //
+ // but we need our own dummy port "myPort" that doesn't exist.
+ // In the short term it works just fine though.
+ initVirtMem = xc->getMemPort();
}
void
@@ -367,6 +381,7 @@ LiveProcess::syscall(ExecContext *xc)
desc->doSyscall(callnum, this, xc);
}
+
LiveProcess *
LiveProcess::create(const string &nm, System *system,
int stdin_fd, int stdout_fd, int stderr_fd,
diff --git a/sim/process.hh b/sim/process.hh
index ffdca819e..68312f115 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -40,27 +40,18 @@
#include <vector>
-#include "arch/isa_traits.hh"
#include "base/statistics.hh"
-#include "base/trace.hh"
-#include "mem/memory.hh"
-//#include "mem/mem_interface.hh"
-#include "mem/page_table.hh"
#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-#include "arch/isa_traits.hh"
class CPUExecContext;
class ExecContext;
class SyscallDesc;
+class PageTable;
class TranslatingPort;
class System;
class Process : public SimObject
{
- protected:
- typedef TheISA::RegFile RegFile;
- typedef TheISA::MachInst MachInst;
public:
/// Pointer to object representing the system this process is
@@ -198,8 +189,7 @@ class LiveProcess : public Process
virtual void syscall(ExecContext *xc);
- virtual SyscallDesc* getDesc(int callnum) { panic("Must be implemented."); }
-
+ virtual SyscallDesc* getDesc(int callnum) = 0;
};
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 667003753..9554ab318 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -48,7 +48,7 @@
#include "base/intmath.hh" // for RoundUp
#include "mem/translating_port.hh"
#include "arch/isa_traits.hh" // for Addr
-
+#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "cpu/base.hh"
diff --git a/sim/system.cc b/sim/system.cc
index 05b41e32b..409e41ead 100644
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -1,12 +1,12 @@
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "cpu/exec_context.hh"
-#include "mem/memory.hh"
#include "sim/builder.hh"
#include "arch/isa_traits.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
#include "base/trace.hh"
+#include "mem/mem_object.hh"
#if FULL_SYSTEM
#include "base/remote_gdb.hh"
#include "kern/kernel_stats.hh"
@@ -228,7 +228,7 @@ DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
- SimObjectParam<Memory *> physmem;
+ SimObjectParam<MemObject *> physmem;
END_DECLARE_SIM_OBJECT_PARAMS(System)
diff --git a/sim/system.hh b/sim/system.hh
index a0ba4f141..0f82f81f5 100644
--- a/sim/system.hh
+++ b/sim/system.hh
@@ -45,7 +45,7 @@ class BaseCPU;
class ExecContext;
class MemoryController;
class ObjectFile;
-class Memory;
+class MemObject;
#if FULL_SYSTEM
class Platform;
@@ -57,7 +57,7 @@ namespace Kernel { class Binning; }
class System : public SimObject
{
public:
- Memory *physmem;
+ MemObject *physmem;
PCEventQueue pcEventQueue;
std::vector<ExecContext *> execContexts;
@@ -146,7 +146,7 @@ class System : public SimObject
struct Params
{
std::string name;
- Memory *physmem;
+ MemObject *physmem;
#if FULL_SYSTEM
Tick boot_cpu_frequency;