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author | Steve Reinhardt <stever@eecs.umich.edu> | 2004-05-17 11:49:46 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2004-05-17 11:49:46 -0700 |
commit | 1d545281b96a6df358201c7b0e610bfaf9e8f213 (patch) | |
tree | 56f869110d789a8efd02a6470b0b74ce718cab68 /sim | |
parent | 32a8827b3ea49fe2c9cd25aa88d7bae2adc6d4e6 (diff) | |
download | gem5-1d545281b96a6df358201c7b0e610bfaf9e8f213.tar.xz |
Significant changes to ISA description to completely factor
out CPU model. ISA description now generates multiple
output source files to (in theory) reduce compilation time.
arch/alpha/isa_desc:
Update for parser changes. Move most constructors
out of class declarations (which are now in decoder.hh)
and into decoder.cc. Move all execute() methods into
exec output.
arch/isa_parser.py:
Significant changes to make ISA description completely
independent of CPU model, and isolate model-dependent parts
of parser into one little class (CpuModel). Also split up code
output into multiple files (a header, a main source file, and
per-cpu execute() method files).
Noticeable changes to language as a result. See updated Doxygen
documentation.
cpu/simple_cpu/simple_cpu.hh:
SimpleCPUExecContext typedef no longer needed.
Add forward declaration of Process.
cpu/static_inst.hh:
SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed.
Make eaCompInst() and memAccInst() return const refs.
--HG--
extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
Diffstat (limited to 'sim')
0 files changed, 0 insertions, 0 deletions